General Instructions
The W681360 is a general-purpose single-channel 13-bit linear pcm codec with 2s complement data format. It is powered by a +3V supply and is available in 20-pin SOG (SOP), SSOP and TSSOP package options. The main function of this device is the digitization and reconstruction of the speech signal, including band limiting and smoothing required by the pcm system. The performance of W681360 is specified over the industrial temperature range -40°C to +85°C.
The W681360 includes an on-chip precision voltage reference. The analog part is fully differential, which reduces noise and improves power supply rejection. The VAG reference pin allows decoupling of the internal circuits that generate the reference voltage to the VSs power supply ground, minimizing clock noise on the analog circuits when external analog signals are referenced to the VSs.
The data transfer protocol supports long and short frames, synchronous and asynchronous communications for pcm applications. The w681360 accepts 8 master clock rates between 256khz and 4.800mhz, and the on-chip prescaler automatically determines the division ratio of the desired internal clock. An additional on-chip power amplifier can drive 300 loads differentially to 3.544V peak-to-peak.
For quick evaluation, a development kit (W681360DK) is available.
For rapid prototyping, a low-cost evaluation board (W681360ES) is also provided.
Features Single +3V Supply (2.7V to 5.25V) – Typical Power Consumption: 9.8MW Standby Power Consumption: 3µW
Power consumption: 0.09 microwatts low noise fully differential analog circuit design
13-bit linear A/D&D/A conversion, using 2s complement data format compliant with ITU G. 712 codec A/D and D/A filtering
8 master clock frequencies of 256kHz
256khz – 4.8mhz bit clock rate on 4.800MHz serial pcm port
On-chip accuracy reference of -5 dBm TLP at 600 (436mVrms) is 0.886 V; Programmable receive gain: 0 to -21dB in 3dB steps Industrial temperature temperature range (–40°C to +85°C)
20-pin SOG (SOP), SSOP and TSSOP and QFN-32L packages offer lead-free/RoHS packaging options for applications
VoIP, Voice over IP equipment Digital telephony and communication systems Wireless voice equipment
DECT/Digital Cordless Phone Broadband Access Device Bluetooth Headset Fiber To The Curb Device Business Phone Digital Voice Recorder Block Diagram

Function description
The W681360 is a single-track single-channel PCM codec for soundtrack applications. The codec conforms to the specifications recommended by ITU-T G.712. The codec block diagram in Section 3 illustrates the main components of the w681360. The chip consists of a pcm interface and can handle both long and short frame sync formats. The chip's prescaler provides the internal clock signal and synchronizes the codec sample rate to the external frame sync frequency. The Power Conditioning block provides internal power for the digital and analog sections, while the Voltage Reference block provides accurate analog ground voltages for analog signal processing.
Calibration levels for analog-to-digital converters (adc) and digital-to-analog converters (dac) refer to the μ-law, weighting zero crossings at the same bit voltage, resulting in a 0dbm0 calibration level 3.2 below the peak sine level db, and then limit according to the reference voltage of 0.886v. At 600Ω, the level is 0.436 Vrms or -5dBm.
W681360 Signal Path

The first stage of the transmission path codec ad path is an analog input op amp with externally configurable gain settings. Differential analog inputs can be applied to inputs ai+ and ai-. Alternatively, the input amplifier can be powered down and a single-ended input signal can be applied to the ao pin or the ai pin. The input amplifier can also determine whether AO or AI+ is selected as input by connecting the ai+ pin to VDD or VSS. When the input op amp is powered down, the AO pin becomes high input impedance.
Input Amplifier Operating Mode When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the analog ground voltage VAG.
The output of the input op amp is first fed through a low pass filter to prevent aliasing at the switched capacitor 3.4khz low pass filter. Subsequently, the 3.4khz switched capacitor low-pass filter bandwidth limits the input signal well below 4khz. Signals above 4kHz will be aliased at a sample rate of 8kHz. A high-pass filter with a 200hz cutoff frequency prevents DC coupling. All filters are designed according to the G.712 ITU-T specification. The high pass filter can be bypassed based on the logic level on the HB pin. If the high pass is removed, the frequency response of the device will extend down to DC.
After filtering, the signal is digitized into a 13-bit linear pcm code and fed to the pcm interface for serial transmission at the sampling rate provided by the external frame sync fst.
Input op amp gain The gain of the input op amp can be adjusted using external resistors. For single-ended input operation, the gain is given by a simple resistor ratio.

Input Op Amp Gain - Single-Ended Input For differential input operation, the external resistor network is more complex, but the gain is expressed in the same way. Of course, differential inputs also have an inherent 6db advantage over their corresponding single-ended inputs.
Input op amp gain - differential input For microphone interface circuits, the gain of the op amp is usually set to 30db. However, gain can be used above 30dB, but this will require a compact layout, minimal trace length and good isolation of noise sources. In addition, it is also recommended that the layout be as symmetrical as possible, work unbalanced to counteract the advantages of noise, and differential designs.
receive path
The 13-bit digital input samples of the d-to-a path are serially shifted and converted into parallel data bits by the pcm interface. In each cycle of the frame sync fsr, the parallel data bits are fed through a 13-bit linear DAC and converted to analog samples. The simulated samples are filtered by a low-pass smoothing filter with a cutoff frequency of 3.4kHz according to the ITU-T G.712 specification. sin(x)/x compensation is integrated with a low-pass smoothing filter. The output of the filter is buffered to provide the receive output signal ro-. The output can also be attenuated when the device is in receive path adjustment mode. If the device is running a half channel with the fst pin clock and the fsr pin held low, the receive filter input will be connected to the vag voltage. This will minimize transients at the RO pin when resuming full channel operation by clocking the FSR pin.
The reverse osmosis output can be connected externally to the PAI pin to provide a differential output with high drive capability on the PAO+ and PAO pins. Various gain settings for this output amplifier can be achieved by using external resistors. If the transmit power amplifier is not in use, it can be turned off by connecting PAI to VDD. The bias voltage and signal reference for the pao+ and pao- outputs are the VAG pins. The VAG pins cannot source or sink current like these pins, so a low impedance load must be placed between Pao+ and Pao-. The pao+ and pao- differential drivers are also capable of driving 100 Ω resistive loads or 100 nF piezoelectric transducers in series with 20 Ω resistors with slightly increased distortion. These drivers can be used to drive 32Ω resistive loads when the gain of pao- is set to 1/4 or less.

Power Management Analog and Digital Power
The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be separated from ground by a 0.1µF ceramic capacitor.
Analog Ground Reference Bypass The system has an internal precision voltage reference that generates a Vdd/2 intermediate supply analog ground voltage. This voltage needs to be separated from vss at the VREF pin by a 0.1µf ceramic capacitor.
Analog Ground Reference Output An analog ground reference can be used as an external reference to the VAG pin. This voltage needs to be separated from vss by a 0.01µf ceramic capacitor. The analog ground reference is generated from the voltage on the VREF pin and is also used for internal signal processing.
pcm interface
The pcm interface is controlled by pins bclkr, fsr, bclkt and fst. Input data is received through the pcmr pin, and output data is sent through the pcmt pin.
Long frame sync or short frame sync interface mode can be selected by connecting the BCLKR or BCLKT pins to a 256kHz to 4.800MHz clock, and connecting the FSR or FST pins to an 8kHz frame sync. The device synchronizes the data word of the pcm interface and the codec sample rate on the positive edge of the frame sync signal. A long frame sync is recognized when the fst pin is held high on two consecutive falling edges of the bit clock of the bclkt pin. A short frame sync mode is identified when the frame sync signal at pin fst is high for one and only one falling edge of the bit clock at pin bclkt.
Long Frame Sync Long frame sync is recognized by the device when the fst pin is held high on two consecutive falling edges of the bit clock at the bclkt pin. The length of the frame sync pulse can vary from frame to frame, as long as a positive frame sync edge occurs every 125 μs. During data transfer in long frame sync mode, the transmit data pin pcmt will become low impedance when the frame sync signal fst is high or when a 13-bit data word is being transmitted. When the frame sync signal fst goes low when sending data or when half lsb is sent, the send data pin pcmt will become high impedance. Internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after each power down state.

Long Frame Sync pcm Mode Short Frame Sync The w681360 operates in short frame sync mode when the frame sync signal at pin fst is high for one and only one falling edge of the bit clock at pin bclkt. On the subsequent bit clock rising edge, the w681360 starts clocking data on the pcmt pin, which will also change from a high impedance state to a low impedance state. The data transfer pin pcmt will return to a high impedance state halfway through the lsb. The w681360's short frame sync operation is based on 13-bit data words. When data is received on the pcmr pin, the data is clocked on the first falling edge after the falling edge coincident with the frame sync signal. Internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after each power down state. The short frame sync mode is shown below. More detailed timing information can be found in the Interface Timing section.
Short frame synchronization (separate clocks for transmit and receive)
Special 16-Bit Receive Mode Sign-Extended Mode Timing When all other clocks are clocked normally, sign-extended mode is entered by applying a logic '0' to the bclkr pin. In standard 13-bit mode, the first bit is the sign bit. In this mode, the device transmits and receives 16-bit data with the sign bit extended to the first four data bits. The powertrain control module timing for this mode is shown below.
PCB sign extension (bclkr=0)
Both transmit and receive use bclkt, the first four data bits are sign bits.
Sign Extension Mode Receive Gain Adjustment Mode Timing Receive path adjustment mode is entered by applying a logic '1' to the bclkr pin when all other clocks are properly clocked. In this mode, the device receives 16 bits of data, where the last three bits are the coefficients used to program the receive gain adjustment attenuation described above. The powertrain control module timing for this mode is shown below.
PCB receive gain adjustment (bclkr=1)
Both sending and receiving use bclkt. fst may happen at a different time than fsr. Bits 14, 15, and 16 are clocked into pcmr for attenuation control of the received analog output.
Receive Gain Adjustment Timing Mode System The timing system can operate at master clock rates of 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz and 4800kHz. The system clock is provided through the master clock input mclk, which can be derived from the bit clock if desired. An internal prescaler is used to generate fixed 256khz and 8khz sample clocks for the internal codec. The prescaler measures the master clock frequency and frame sync frequency and sets the division ratio accordingly. If both frame syncs are low for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, then
The W681360 will enter a low power standby mode. Another way to power off is to set the pui pin low. When the system needs to be powered up again, the pui pin needs to be set high and there needs to be a transmit frame sync pulse. Two transmit frame sync cycles are required before pin pcmt becomes low impedance.
On-Chip Power Amplifiers On-chip power amplifiers are typically used to drive external speakers. The inverting input of the power amplifier is available on the pin pai. The non-inverting input is internally connected to VAG. The inverter output pao- is used to provide a feedback signal to the pai pin to set the gain of the power amplifier outputs (pao+ and pao-). These push-pull outputs are capable of driving 300Ω loads
V peak.
Connecting PAI to VDD will turn off the power driver amplifier and the PAO+ and PAO- outputs will have high impedance.

Timing diagram

Typical Application Circuit