feature

Logically 4-kbit Ferroelectric Random Access Memory (F-RAM) organized by 512 x 8 High Endurance 10 Trillion ( 1013 ) Read/Write 121 Year Data Retention Period (see Data Retention and Endurance Table) nodelay 8482 ; Write Into advanced high reliability ferroelectric process Very fast Serial Peripheral Interface (SPI) up to 14 MHz Direct replacement for Serial Flash and EEPROM Hardware Support for SPI Mode 0 (0, 0) and Mode 3 (1, 1) Complex Write Protection Scheme Hardware Protection Using Write Protect (WP) Pin Software Protection Using Write Disable Instruction Software Block Protection of 1/4, 1/2, or Entire Array Low Power Consumption 300 μA Active Current 10 μA at 1 MHz (typ. value) Standby current at +85°C Voltage operation: VDD=4.5 V to 5.5 V Auto-E temperature: –40°C to +125°C 8-pin Small Outline Integrated Circuit (SOIC) package compliant with AEC Q100 1 Grade standards compliant with Restriction of Hazardous Substances (RoHS)

Function description

The FM25040B is a 4-kbit non-volatile memory using an advanced ferroelectric process. Ferroelectric random access memory or f-ram is non-volatile and performs read and write operations. Similar to a ram. It provides 121 years of reliable data retention while eliminating the complexity, overhead and reliability issues caused by system-level serial flash, eeprom and other non-volatile memory. Unlike serial flash and eeprom, the fm25040b performs writes at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been successfully transferred to the device. The next train can start without data polling. Also, this product has a sizable write-persistent non-volatile memory compared to other products. The FM25040B is capable of supporting 1013 read/write cycles, or more than EEPROM. These features make the fm25040b ideal for non-volatile. In-memory applications that require frequent or fast writes. Examples include data collection, where cycles may be critical where industrial control is required, serial flash or long write times for eeproms can result in data loss. The FM25040B offers a huge benefit to serial users of EEPROM or flash memory as a hardware replacement. This FM25040B adopts high-speed SPI bus, which enhances the high-speed write capability of f-ram technology. Device specifications warrant a temperature range of -40°C to +125°C over the automotive-E temperature range.

Functional Overview

The FM25040B is a serial F-RAM memory. The memory array is logically organized as 512 x 8 bits using the industry standard Serial Peripheral Interface (SPI) bus. The functional operation of this F-RAM is similar to that of serial flash and serial EEPROM. The main difference between the FM25040B serial flash or EEPROM with the same pinout is that the f-ram has excellent write performance, high endurance and low power consumption. The FM25040B differs from Cypress's fm25040 by increasing its performance to 14mhz and adding support for SPI mode 3. This makes the fm25040b a replacement for most supported modes of 4-kbit SPI EEPROMs 0 and 3. Memory Structure When accessing the fm25040b, the user address is 512 locations of 8 data bits each. These eight data shift bits go in and out continuously. Use the SPI access address protocol, including chip select (allowing multiple devices on the bus), an opcode containing the upper address bits, and word addresses. The word address consists of the following 8 address bits. The 9-bit full address specifies the address of each byte uniquely. Most of the functions of the FM25040B are handled by the SPI control interface or by the on-board circuitry. Access time memory operations are essentially zero, and serial protocols are required over time. That is, the memory is read or written at the speed of the spi bus. Unlike serial flashes or EEPROMs, there is no need to poll the device for a ready condition because writes happen at bus speed. A write operation has completed when a new bus transaction can be transferred to the device. This is explained in more detail in the interface section.

Note: The FM25040B does not contain power management circuitry other than a simple internal power-on reset circuit. It is the user's responsibility to ensure that VDD is within the data sheet tolerance to prevent erroneous operation. It is recommended that the part is not powered off when the chip is activated. Serial Peripheral Interface - SPI Bus The FM25040B is an SPI slave device that operates up to 14 MHz faster. The high-speed serial bus provides high-performance serial communication to the SPI host. Many common microcontrollers have hardware SPI ports that allow direct interfacing. Use the normal port pins of the microcontroller. This FM25040B works in SPI mode 0 and 3. SPI Overview SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins. SPI is a synchronous serial interface that uses clock and data pins for memory access and supports multiple devices on the data bus. Devices on the SPI bus use the CS active pin. The relationship between chip select, clock and data is through spi mode. This device supports SPI modes 0 and 3. In both modes, data is recorded to the F-RAM on the rising edge of the SCK starting from the first rising edge after CS is active. The spi protocol is controlled by opcodes. These opcodes specify commands from a bus master to a slave. After activating CS, the first byte transferred from the bus master is the opcode. Depending on the opcode, any address and then transfer data. CS must complete the operation before a new opcode can be issued. The terms commonly used in the spi protocol are as follows: The master spi master device controls operations on the spi bus. An SPI bus may have only one master node and one or more slave node devices. All slaves share the same SPI bus. The master can use the cs pin to select any slave. All operations must be activated by the slave device by pulling the CS pin of the slave device low. The master also generates all data transfers on sck and si so the line is synchronized with this clock. The SPI Slave Master activates the SPI Slave select line via the chip. The slave device gets sck from the spi as input to the master and all communication is clocked with this. The spi slave never starts the communication bus on the spi and only operates on the instructions of the master. The fm25040b operates as a spi slave and can share the bus of the spi and other spi slave devices. Chip Select (CS) To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued to the slave device only when the CS pin is low. When the device is not selected, data passing through the si pin is ignored and the serial output pin (SO) remains in a high impedance state. Note: New instructions must start from the falling edge of CS. Therefore, only one opcode selection "loop" can be issued per active chip. Serial Clock (SCK) After the serial clock is run by the SPI master and CS, the communication is synchronized low with this clock. FM25040B enables SPI mode 0 data transfer (si/so) The spi data bus consists of two serial data lines si and so to communicate. si is also called master out slave in (mosi) so it is called master slave out (miso). The master issues commands to the slave via the si pin, and the slave responds via the SO pin. Multiple slave devices can share the si and so lines described earlier. The fm25040b has two separate si and so pins that can be connected to the host. For microcontrollers that do not have a dedicated SPI bus, a general-purpose port can be used. To reduce resources on the hardware controller, you can connect the two data tie pins (si, so) together, and tie the fixed and wp pins together. The diagram shows such a configuration, which uses only three pins. Most Significant Bit (msb) The spi protocol requires that the first bit transmitted is the most significant bit (msb). This pairs address and data transfers. 4-kbit serial f-ram requires an opcode, including address bits, and a word address for any read or write operation. The word address consists of the lower 8-bit address. This 9-bit full address uniquely specifies each byte address. After the serial opcode selects the slave, CS goes low and the first byte received is considered the opcode for the intended operation. The fm25040b uses standard opcodes for memory access. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of CS and the SO pin remains tri-stated. Status Register FM25040B has an 8-bit status register. The bit register in Status is used to configure the device.

SPI mode

The FM25040B can be driven by a microcontroller with SPI. Peripherals operate in one of two modes: spi mode 0 (cpol=0, cpha=0) spi mode 3 (cpol=1, cpha=1) for both modes , the input data is latched on the rising edge of the SCK starting from the first rising edge after CS is active. If the clock starts from a high state (mode 3), the first one considers the rising edge after the clock switch. Output data is available on the falling edge of SCK. The two SPI modes to transfer data are: Mode 0 when SCK is held at 0 Mode 3 SCK is held at 1 The device detects the SPI mode from the state of the SCK pin when the device is selected by lowering the CS pin. If the SCK pin is low when the device is selected, SPI mode 0 is assumed to be high, and the SCK pin is assumed to be high, operating in SPI mode 3.

wren - Set write enable latch FM25040B will power up with write disabled. Wren commands must be issued before any write operations. Sending the wren opcode allows the user to issue subsequent opcodes for write operations. These include writing to the status register (wrsr) and writing to memory (write). Sending the wren opcode causes an internal write enable to set the latch. A flag bit in the status register, called WEL, indicates the state of the latch. wel='1' means writing is allowed. Attempting to write to the WEL bit in the status register has no effect on the state of that bit - only the wren opcode can set this bit. The WEL bit will automatically clear the cs edge after a wrdi, wrsr or write operation when rising. This prevents further writes to the Status Register or F-RAM array without another wren command. Figure illustrates the wren command bus configuration. Note: The FM25040B section does not clear memory locations from 0x100 to 0x1FF (write) operations after the Write Enable Latch (WEL) bit in the Status Register performs a memory write.

memory operation

The SPI interface, which can provide high clock frequencies, highlights the fast write capability of F-RAM technology. Unlike serial flash and eeprom, the fm25040b can perform sequential writes at bus speed. Any number of sequential writes can be performed without page registration. Write Operations All operations that write to memory begin with the wren opcode. The write opcode includes the upper bits of the memory address. The bit 3 opcode corresponds to the upper address bit (A8). The next byte is the lower 8 bits of the address (a7-a0). A total of 9 bits specify the address of the first byte of the write operation. Subsequent bytes are data bytes written in sequence. The address is incremented internally as long as the bus master continues to issue clocks and keep CS low. If the last address reaches 1FH, the counter will roll over to 000h. Data is written to msb first. The rising edge of cs terminates the write operation. Note that when a burst write reaches a protected block address, automatic address increment stops and all subsequent data devices ignore the bytes received for the write. eeprom uses page buffers to increase its write throughput. This makes up for the slow write operation inherent in the technology. F-RAM memory does not have a page buffer because each byte is written to the f-ram array as soon as it finishes clocking in (after eight). This allows any number of bytes to be written without page buffer latency. Note that if power is lost during a write operation, only the last completed byte will be written. Read operations The bus master can issue a read opcode after the falling edge of CS. The read opcode includes the upper address of the memory where bit 3 of the opcode corresponds to the upper address bit (A8). The next byte is the lower 8 bits of the address (a7-a0). In total, 9 bits specify the address operation of the first byte read. After the opcode and address are issued, the device outputs the read data on the next eight clocks. SI input is ignored when reading data bytes. Subsequent bytes are data bytes, and addresses are read out in order as long as the bus master continues to issue clocks and CS low. If the last address of 1FH is reached, the counter will roll back to 000h. First read msb data. The rising edge of cs terminates the read operation and tri-states the SO PIN.