Function description

LMH0046 HD/SD SDI re -locking time sequence support SMPTE 292M and SMPTE 259m (A AMP; AMP; C) The serial digital video standard conforms to SMPTE 292M digital video data and SMPTE 259m ( A amp; amp; c) standard. LMH0046 supports 143 Mbps, 270 Mbps, 1.483 Gbps, runs with serial data rates of 143 Mbps, 270 Mbps, and 1.485 Gbps serial data rate operations 1.483 GBPS and 1.485 GBPS. LMH0046 supports DVB-ASI with 270 Mbps and supports DVB-ASI operations at a rate of 270 Mbps. A single 3.3V power operation LMH0046 automatically detects the typical power consumption data rate of 330 MW, and adjusts itself to input data with cumulative jitter at a timely time. Lmh0046 Two differentials, heavy lock output recovery serial data rate clocks Select the second heavy lock output or low-as the output. LMH0046 has two jitter, differential, data rate clock output negative serial data output; the second output can choose a single 27 MHz external crystal or benchmark as a low jitter and a data rate clock output. The clock input control and indicator lights are: serial clock or second serial data output selection, the manual rate selects input, the manual rate selects the SD/HD rate indicator output, locks the detection output, the SD/HD operating rate indicator output automatic/automatic/ Manual data bypass and output mute. The serial number lock the detection index output data input, output and serial data rate clock output is compatible with differential LVPECL. Chronic granulocyte leukemia

Data and the output of the clock output mute function serial data and serial data rate clock output

It is suitable for automatic/manual re -closing of the driver's 100Ω differential terminal connection [ 123]

[12]3] - Video standards and format converters

AC electrical characteristics

Power supply voltage and working temperature range are too large, unless there are other regulations. (1)

(1) The typical value is: VCC u003d+3.3V, TA u003d+25 ° C.

(2) According to SMPTE RP 184-1996, the sinusoidal mission peak amplitude of the sine. Test data signals should be color strips.

(3) Reference ""A1"" in FIG. 1 in FIG. 1 of SMPTE RP 184-1996.

(4) It is characterized by the limitations of SDI testing equipment.

(5) This parameter is determined by describing the voltage and temperature limit.

(6) Reference ""A2"" in FIG. 1 in FIG. 1 of SMPTE RP 184-1996.

(7) The serial data output jitter is 0.2UIP-P input the total output jitter.

AC electrical characteristics (continued)

The power supply voltage and working temperature range are too large, unless there are other regulations. (1)

(8) Specifications are guaranteed by design.

(9) Start measurement from the first SDI conversion until the lock detection (LD) output becomes high (true).

(10) RL u003d 100 Differential.

Device description

LMH0046 HD/SD-SDI heavy unlocking device for multiple digital video signal processing devices. The supporting serial digital video standards are SMPTE259M (A AMP; AMP; C) and SMPTE 292M. The corresponding serial data rates are 143 Mbps, 270 Mbps, 1.483 Gbps, and 1.485 Gbps, respectively. The DVB-ASI data of 270 Mbps can also be redirected. LMH0046 Reset the serial data stream to inhibit cumulative jitter. It provides two low jitter, differential, serial data output. You can choose the second output to output serial data or low shake serial data rate clock. Control and indicator lights include: serial data rate clock or second serial data output selection, manual rate selection input, SD/HD rate output, lock detection output, automatic/manual data bypass and output mute. Serial data input is compatible with CML and LVPECL. The serial data and data rate clock output is the differential CML and generate the LVPECL compatibility level. The output buffer design can drive AC or DC coupling, connecting 100 different mobilization load. In 100 communication or DC coupling combined load, the differential output level is 800 MVP-P ± 10%. Logic input and output are compatible with LVCMOS. This device package is a 20 -shot HTSSOP and exposed mold connection pad. The exposed mold connection pad electrical connection to the device ground (VEE) is the negative electrical terminal of the device. This terminal must be connected to the negative power supply or circuit ground. Serial data input, serial data, and clock output serial data input and output deviation serial data input SDI to receive serial digital video data specified in Table 2. The serial number data input is compatible with differential LVPECL. The input is aimed at the adaptive cable equalizer such as LMH0034. Input is not internal terminal or biased. If an appropriate input bias voltage is provided, the input can be coupled. Figure 4 shows the equivalent input circuit of SDI and SDI. LMH0046 has two redo -time difference serial data output SDO and SCO/SDO2. These outputs provide low jitter, differential, timing data to device, such as LMH0002 cable drive or LMH0031 back serialization. Output SCO/SDO2 is reused by multiple paths, which can provide a second serial data output or serial data rate clock output. Figure 5 shows the equivalent output circuit of SDO, SDI, SCO/SDO2 and SCO/SDO2. SCO_en input controls the working mode of SCO/SDO2 output. When the SCO_EN inputs high, the SCO/SDO2 output provides a serial data rate clock. When the SCO_EN is low, the SCO/SDO2 output provides timed serial data. When the mute input is a logical low power, the two differential serial data output SDO and SCO/SDO2 are mute. When this output runs as a serial clock, when the bypass mode is activated, the SCO/SDO2 will also silently output. When mute, SDO and SDO (or SDO and SDO) will use the opposite differential output level. This CML serial data output is compatible with differential LVPECL. These outputs have internal 50 and are suitable for driving communication or DC coupling.

Operating serial data rate

The device works with serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps, and 1485 Mbps. This device can not lock the harmonics of these rates. This device does not lock and automatically enters the data rate of data below the overcurrent bypass: 177 Mbps, 360 Mbps, and 540 Mbps. Serial data clock/serial data 2 output serial data clock/serial data 2 output is controlled by the SCO 帴 EN input, and provides a one -second redirection serial data output or a low shake differential clock output processing suitable for serial data rate Essence When the output of the serial clock is running, the rising edge of the clock will be within 10%of the data interval centerCorresponding serial data bit interval. When the SCO_en input is low in logic, the differential output SCO/SDO2 is used as the second serial data output level. When the SCO_EN input is a logical high, the output is used as a serial data rate clock output. This SCO IU EN Input has an internal drop -down device. The default state of SCO 峎 EN is LOW (serial data output 2 has been enabled). When the mute input is a logical low power, SCO/SDO2 is mute. When the bypass mode is activated, this output is used as a serial clock output, and the output will be mute.

Serial data rate selector

Serial data rate selector (rate [1: 0]) allows users to fix the serial data rate. The internal drop -down menu that keeps logic is low input, unless the external drive is high to the logic high state. This input is also used to place the device in the test mode. The code displayed in Table 2 Select the required operating serial data rate. LMH0046 then entered the automatic rate detection mode or a single operating rate. When re-locking the DVB-ASI data, you can also select the 270 Mbps rate mode. DVB-ASI data is encoded data transmitted by 8B10B encoded. The device will lock the data without harmonious locking. The automatic rate detection mode can be used for any support data rate, including DVB-ASI.

Lock detection

When the output of the lock detection (LD) is high, it means that the data is receiving the data, and the PLL has been locked. LD may be connected to the mute input, and the data and clock output are silent when the data signal is not received. Do you see it? Table 3.

Silent

Silent input, when low, mute serial data and clock output mute. It can be connected to the lock detection or external drive to make the output mute or cancel the mute. If the mute is connected to the LD, the data and clock output will be mute when the PLL is not locked. This function covers bypass function: see Table 3. There is an internal pull -up device that enables the output under default.

Wing/automatic bypass

When the bypass/automatic bypass input is high, the mandatory device outputs data without locking again. When is the input low, when the device is unlocked, the device automatically bypass the functional conditions of the heavy gates or the detected data rate is the rate that the device does not support. See Table 3. There is an internal drop -down device on bypass/automatic bypass.

SD/HD

SD/HD output indicator LMH0046 is processing SD or HD data rate. It can be used to control another device, such as the LMH0002 cable drive. When the output is high, the data rate is 270Mbps (or 143 Mbps). When low, the indicated data rate is 1483 or 1485 Mbps. SD/HD output is a registered function and is effective when locking the loop and locking output is high. When the PLL is not locked (the lock detection output is low), the SD/HD output defaults to HD (low). The SD/HD output is not defined due to the data rate on the SDI, lock the detection assertion or cancel the short time after the assertion. The time arrangement is shown in Figure 6 to show a chart between SDI, lock detection and SD/HD.

TACQ u003d collection time, define

t1 u003d from lock detection assertion or cancellation assertion to SD/HD output valid time It is usually 37 nanoseconds (a clock cycle of 27 MM)

T2 u003d enter the time from SDI to the lock detection to cancel the assertion, the longest 1 milliseconds. SD/HD output is invalid during this period.

Input SCO_EN to make the SCO/SDO2 differential output can be used as a serial data rate clock or second serial data output. The role of SCO/SDO2 starts serial data rate clock when SCO 峎 EN is higher. There is an internal pull -down device. The default state (low) enables SCO/SDO2 output as the second serial data output.

Crystals or external clock bases are allowed

LMH0046 Use 27 MHz crystal or external clock signal as a regular reference input. 27MHz parallel resonance crystals and load networks can be connected to the XTAL IN/EXT CLK and XTAL OUT pin. Alternatively, you can input 27MHz LVCMOS compatible clock signals to XTAL IN/EXT CLK. A parameter 4 gives the appropriate crystal.

FIG. 7 shows LMH0046 and LMH0034 SMPTE 292M/259M adaptive circuit cable equalizer and LMH0002 SMPTE 292m/259m cable drive.