General Instructions
The W77I058 is a fast 8051 compatible microcontroller with a redesigned processor core with no wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the original 8051 at the same crystal speed. Typically, the instruction execution time of the w77i058 is 1.5 to 3 times faster than the legacy 8051, depending on the type of instruction. Generally speaking, at the same crystal speed, the overall performance is about 2.5 times higher than the original. At the same throughput, the clock speed is reduced and the power consumption is increased. Therefore, the W77I058 is a fully static CMOS design; it can also operate at lower crystal clocks. The W77I058 contains 32 kb Flash EPROM and provides an operating voltage from 2.7V to 5.5V. All W77I058 types also support on-chip 1 kb SRAM without external memory components and glue logic, which can save more I/O pins for applications if users use on-chip SRAM instead of external SRAM.
feature
8-bit CMOS microcontroller
4 clocks/machine cycle high-speed architecture up to 20 MHz
Standard 80C52 compatible pinout MCS-51 compatible instruction set Four 8-bit I/O ports One additional 4-bit I/O port and wait state control signals (available on 44-pin PLCC/QFP package)
Three 16-bit timers
12 interrupt sources with two priority levels On-chip oscillator and clock circuitry Two enhanced full-duplex serial ports
32 KB Flash EPROM
256 bytes of Notepad RAM
1kb on-chip sram for movx instructions
Programmable Watchdog Timer Dual 16-bit Data Pointers Software Programmable Access Cycle Wrapper for External RAM/Peripherals:
- Lead Free (RoHS) Dipping 40: W77I058A25DL
- Lead-free (RoHS) PLCC 44: W77I058A25PL
Pin configuration

Function description
W77I058 is pin compatible with 8052 and compatible with instruction set. It includes standard 8052 resources such as four 8-bit I/O ports, three 16-bit timers/counters, a full-duplex serial port, and interrupt sources.
The W77I058 features a faster, better-performing 8-bit CPU with no wasted clock and memory cycles from a redesigned core processor. Not only does it improve performance by running at high frequencies, but it also improves performance by reducing machine cycles for most instructions from the standard 8052 cycle of 12 clocks to 4 clock cycles. This will increase performance by an average of 1.5 to 3 times. The w77i058 also provides double data pointers (dptrs) to speed up block data memory transfers. It also adjusts the duration of MOVX instructions (accessing off-chip data memory) between two machine cycles and nine machine cycles. This flexibility allows the W77I058 to work efficiently on high-speed and low-speed RAM and peripherals. In addition, the W77I058 contains a 1KB MOVX SRAM chip with addresses between 0000H and 03FFH. It can only be accessed via the movx instruction; this on-chip SRAM is optional under software control.
The W77I058 is an 8052 compatible device that provides users with the functionality of the original 8052 device, but with improved speed and power consumption characteristics. Its instruction set is the same as the 8051 series, with only one addition: dec dptr (opcode a5h, dptr is decreased by 1). While the original 8051 series was designed to operate at 12 clock cycles per machine cycle, the W77I058 operates at a significantly lower clock frequency with only 4 clock cycles per machine cycle. This naturally speeds up the execution of instructions. So even with the same crystal, the w77i058 can run at higher speeds than the original 8052. Since the w77i058 is a fully static CMOS design, it can also operate at a lower crystal clock, providing the same throughput in terms of instruction execution while reducing power consumption.
The 4 clocks per machine cycle feature in the W77I058 enables three times the execution speed. The W77I058 has all the standard features of the 8052, plus some additional peripherals and features.
Input and output ports
The W77I058 has four 8-bit ports and an additional 4-bit port. Port 0 can be used as an address/data bus when an external program is running or when MOVC or MOVX instructions are accessing external memory/devices. In these cases, it has strong pull-ups and pull-downs and doesn't require any external pull-ups. Otherwise, it can be used as a general-purpose I/O port with open-drain circuitry. When port 0 is used as the address/data bus, port 2 is mainly used as the upper 8 bits of the address bus. It also has strong pull-up and pull-down capabilities when used as an address bus. Ports 1 and 3 act as I/O ports with alternate functions. Port 4 is only available on the 44-pin PLCC/QFP package type. it is a common use
The I/O ports act as port 1 and port 3. p4.0 has an alternate function wait, which is the wait state control signal. When the wait state control signal is enabled, only P4.0 is input.
Serial input and output
The W77I058 has two enhanced serial ports that function similarly to the serial ports of the original 8052 series. However, the serial port on the w77i058 can also work in a different mode for timing similarity. Note that serial port 0 can use either timer 1 or 2 as a baud rate generator, but serial port 1 can only use timer 1 as a baud rate generator. The serial port has enhancements for automatic address recognition and framing error detection.
timer
The W77I058 has three 16-bit timers, which function similarly to the 8052 series timers. When used as timers, they can be set to run at 4 clocks or 12 clocks per count, giving the user the option to operate in a mode that emulates the timing of the original 8052. The W77I058 has an additional function, a watchdog timer. This timer is used as a system monitor or a very long period timer.
interrupt
The interrupt structure of the W77I058 is slightly different from the standard 8052. The number of interrupt sources and interrupt vectors has increased due to additional functions and peripherals. W77I058 provides 12 interrupt resources with two priority levels, including 6 external interrupt sources, timer interrupt, serial I/O interrupt.
Data pointer The original 8052 has only one 16-bit data pointer (dpl, dph). In w77i058, there is an additional 16-bit data pointer (dpl1, dph1). This new data pointer uses two sfr locations that were not used in the original 8052. There is also an additional instruction, dec dptr (opcode a5h), which helps increase user programming flexibility.
Power Management Like the standard 80C52, the W77I058 also has idle and power-down modes of operation. The W77I058 offers a new economy mode that allows the user to divide the internal clock rate by 4, 64 or 1024 . In idle mode, the clock to the CPU core is stopped while the timer, serial port and interrupt clocks continue to operate. In power-down mode, all clocks are stopped and chip operation is completely stopped. This is the lowest power state.
On-chip data sram
The w77i058 has 1k bytes of data space sram that can be read/written and is memory mapped. The on-chip movx sram is implemented by the movx instruction. It is not used for executable program memory. There is no conflict or overlap between 256 bytes of scratchpad ram and 1k bytes of movx sram because they use different addressing modes and separate instructions. On-chip movx SRAM is enabled by setting the dme0 bit in the pmr register. After reset, the dme0 bit is cleared so that the on-chip movx sram is disabled and all data memory spaces 0000h-ffffh access external memory.
6. memory organization
The W77I058 divides the memory into two separate parts: program memory and data memory. Program memory is used to store instruction opcodes while data memory is used to store data or for memory mapped devices.
program memory
Program memory on the W77I058 can be up to 64 KB. There are also on-chip roms that can be used similar to the 8052, except that the size of the rom is 32kbytes. All instructions are fetched and executed from this memory area. The movc instruction can also access this memory area. Exceeding the maximum address of the on-chip rom will access external memory.
data storage
The W77I058 can access up to 64KB of external data memory. This memory area is accessed by the movx instruction. Unlike the 8051 series, the w77i058 contains 1k bytes of movx sram data memory, which can only be accessed by movx instructions. The 1K bytes of SRAM are between addresses 0000H and 03FFH. Access to on-chip movx sram is optional under software control. When enabled via software, any movx instruction that uses this area will go into the on-chip ram. movx addresses greater than 03ffh automatically go to external memory via ports 0 and 2. When disabled, the 1KB memory region is transparent to the system memory map. Any movx pointing to the space between 0000h and ffffh goes to the expansion bus on ports 0 and 2. This is the default condition. Additionally, the w77i058 has standard 256-byte on-chip scratchpad ram. This can be accessed by direct or indirect addressing. There are also some special function registers (sfr), which can only be accessed by direct addressing. Because scratchpad ram is only 256 bytes, it can only be used when the data content is small. If there is a large data content, two options are available. One is on-chip movx sram and the other is external data memory. On-chip movx sram can only be accessed by movx instructions, same as external data memory. However, on-chip ram has the fastest access times.

special function register
The W77I058 uses Special Function Registers (SFRs) to control and monitor peripherals and their modes.
sfr is located in register location 80 ffh and is only accessed by direct addressing. Some SFRs are bit addressable. This is useful when you want to modify a specific bit without changing other bits. Bit-addressable SFRs are those whose addresses end in 0 or 8. The W77I058 contains all the SFRs in the standard 8052. However, some additional SFRs are also added. In some cases, unused bits in the original 8052 were given new functions. The list of SFRs is as follows. The table contains eight positions per row. Empty locations indicate that these addresses have no registers. It will read high when a bit or register is not implemented.

instruction time
The instruction timing of the w77i058 is an important aspect, especially for those who wish to use software instructions to generate timing delays. Additionally, it provides users with insight into the timing differences between the w77i058 and the standard 8032. In the W77I058, there are four clock cycles per machine cycle. Each clock cycle is designated as a state. Thus, each machine cycle consists of four states c1, c2, c3, and c4 in sequence. Both clock edges are used for internal timing due to the reduced time each instruction takes to execute. Therefore, the duty cycle of the clock must be as close to 50% as possible to avoid timing conflicts. As mentioned, the w77i058 performs an opcode fetch per machine cycle. Therefore, in most instructions, the number of machine cycles required to execute the instruction is equal to the number of bytes in the instruction. Of the 256 available opcodes, 128 are single-cycle instructions. Therefore, more than half of the opcodes in the w77i058 are executed in only four clock cycles. Most two-cycle instructions are instructions with a two-byte instruction code. However, some instructions are only one-byte instructions, but they are two-cycle instructions. An important instruction is the movx instruction. In the standard 8032, MOVX instructions are always two machine cycles long. However, in w77i058 the user has a tool to cycle the duration of this instruction from machine to 9 machine cycles. The rd and wr strobe lines are also proportionally extended. This gives users flexibility in accessing fast and slow peripherals with no external circuitry and minimal software overhead. The remaining instructions are three, four or five machine loop instructions. Note that in the W77I058 there are five different types depending on the number of machine cycles, while in the standard 8032 there are only three. However, in the w77i058, each machine cycle consists of only 4 clock cycles compared to the standard 8032's 12. Therefore, even with the increased number of classes, each instruction is at least 1.5 to 3 times faster than the standard 8032 in terms of clock cycles.

MOVX instruction
The W77I058, like the standard 8032, uses MOVX instructions to access external data memory. The data memory includes off-chip memory and memory-mapped peripherals. While the result of the movx instruction is the same as the standard 8032, the operation and timing of the strobe signal has been modified to give the user more flexibility.
There are two types of movx instructions, movx@ri and movx@dptr. In movx@ri, the addresses of external data come from two sources. The lower 8 bits of the address are stored in the ri register of the selected working register bank. The upper 8 bits of the address come from the Port 2 SFR. In the movx@dptr type, the full 16-bit address is provided by the data pointer.
Since the w77i058 has two data pointers dptr and dptr1, the user must choose between the two by setting or clearing the dps bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR and is present at position 86H. The other bits in this SFR have no effect, and they are set to 0. When dps is 0, dptr is selected, and when it is set to 1, dptr1 is selected. The user can switch between dptr and dptr1 by toggling the dps bit. The fastest way is to use the inc instruction. The advantage of having two data pointers is most apparent when performing block move operations. The accompanying code shows how using two separate data pointers can speed up the execution time of code that performs the same task.

power management
The W77I058 has several features that help the user control the power consumption of the device. The power saving features are basically a power-off mode, an economy mode, and an idling operation mode.
Idle Mode The user can put the device into idle mode by writing 1 to bit pcon.0. The instruction that sets the idle bit is the last instruction executed before the device enters idle mode. In idle mode, the clock to the CPU is halted, but the clocks to the interrupts, timers, watchdog timers, and serial port blocks are not halted. This will force the CPU state to freeze; the program counter, stack pointer, program status word, accumulator and other registers save their contents. In the idle state, the ale and psen pins are held high. Port pins hold the logic state when idle is activated. Idle mode can be terminated in two ways. Since the interrupt controller is still active, activating any enabled interrupt can wake up the processor. This will automatically clear idle bits, terminate idle mode, and execute the Interrupt Service Routine (ISR). After the ISR, the program will resume execution from the instruction that put the device into idle mode.
Idle mode can also be exited by activating a reset. The device can be reset by applying a high voltage to the external RST pin, a power-on reset condition, or a watchdog timer reset. The external reset pin must be held high for at least two machine cycles, i.e. 8 clock cycles to be considered a valid reset. In a reset condition, the program counter is reset to 0000h and all SFRs are set to the reset condition. Since the clock is already running, there is no delay and execution starts immediately. In idle mode, the watchdog timer continues to run, and if enabled, a timeout will cause a watchdog timer interrupt, which will wake up the device. Software must reset the watchdog timer in order to preempt the reset that occurs after a 512 clock cycle timeout. When the w77i058 exits from idle mode via reset, the instructions following the instruction to put the device in idle mode will not execute. So there is no danger of accidental writing.
economic model

The power consumption of the microcontroller is related to the operating frequency. The W77I058 offers an economy mode that dynamically reduces the internal clock rate without the use of external components. By default, one machine cycle takes 4 clocks. In economy mode, software can select 4, 64 or 1024 clocks per machine cycle. It keeps the CPU running at an acceptable speed but eliminates power consumption. In idle mode, the clock to the core logic is stopped, but all clocked peripherals (such as watchdog timers) still run at the rate of clock/4. In economy mode, all clocked peripherals run at the same reduced clock rate as the core logic. Therefore, eco mode may provide lower power consumption than idle mode.

By writing 1 to bit pcon.1, the device can enter power-down mode. The instruction to do this will be the last instruction executed before the device enters shutdown mode. In power-down mode, all clocks are stopped and the device is stopped. All activity ceases completely and power consumption is reduced to the lowest possible value. in this case
The PSEN pin is pulled low. The port pins output the value of their respective sfr.
The W77I058 will exit power-down mode by reset or by enabling an external interrupt pin that is level-detected. An external reset can be used to exit a shutdown state. A high level on the RST pin terminates power-down mode and restarts the clock. Program execution will resume at 0000h. In power-down mode, the clock is stopped, so the watchdog timer cannot be used to provide a reset to exit power-down mode.
The W77I058 can wake up from power-down mode by forcing activation of an external interrupt pin, provided that the corresponding interrupt is enabled, the global enable (EA) bit is set, and the external input is set to level detect mode. If these conditions are met, a low level on the external pin restarts the oscillator. The device then executes the interrupt service routine for the corresponding external interrupt. After the interrupt service routine completes, program execution returns to the instructions that put the device into power-down mode and resume execution from that mode. When the rgsl(exif.1) bit is set to 1, the cpu will use the internal rc oscillator instead of the crystal to exit power-down mode. Once the clock is stable, the microcontroller will automatically switch from the rc oscillator to the crystal. The operating frequency of the rc oscillator is about 2-4mhz. Using the rc oscillator to exit power-down mode saves time waiting for the crystal to start up. It is useful in low-power systems, typically waking up from a short period of operation and then returning to power-down mode.

Reset Conditions The user has several hardware-related options for placing the W77I058 in a reset state. In general, most register bits go to their reset value regardless of the reset condition, but there are some flags whose state depends on the source of the reset. Users can use these flags to determine the reason for using a software reset. There are two ways to get the device into a reset state. They are external reset and watchdog reset.
Externally reset the device continuously samples the first pin in the C4 state of each machine cycle. Therefore, the RST pin must be held for at least 2 machine cycles to ensure that a valid RST high is detected. The reset circuit then applies the internal reset signal synchronously. Therefore, reset is a synchronous operation and requires a clock to run to cause an external reset.
Once the device is in reset, it will remain the same as long as rst is 1. Even after rst is deactivated, the device will continue to be in reset for two machine cycles before program execution starts at 0000h. There are no flags related to external reset conditions. However, since the other two reset sources have flags, if these two flags are cleared, the external reset can be considered the default reset.
The por flag must be cleared after being read by software, otherwise the source of future resets will not be correctly determined. In the event of a power failure, i.e. below VRST, the device will go into reset again. When power returns to the correct operating level, the device will again perform the power-on reset delay and set the por flag.
The Watchdog Timer is a free-running timer with a programmable time-out interval. The user can clear the watchdog timer at any time to restart counting. When the timeout interval is reached, the interrupt flag will be set. If the watchdog reset is enabled and the watchdog timer is not cleared, the watchdog timer will generate a reset 512 clocks from the flag being set. This will put the device into a reset state. The reset condition is maintained by hardware for two machine cycles. Once the reset is removed, the device will start executing from 0000h.
Most SFRs and registers on a reset state device will go to the same state in reset state. The program counter is forced to 0000h and remains there as long as the reset condition is applied. However, the reset state does not affect the on-chip ram. During reset, the data in RAM will be retained. However, the stack pointer is reset to 07h, so the stack contents are lost. If VDD falls below about 2V, RAM contents will be lost, as this is the minimum voltage level required for RAM to function properly. Therefore, after the first power-on reset, the RAM contents will be indeterminate. In the event of a power outage, if the power supply falls below 2V, the RAM contents will be lost.
After reset, most SFRs are cleared. Interrupts and timers are disabled. If the reset source is por, the watchdog timer will be disabled. ffh is written in port sfr, thus making the port pin high. Port 0 is floating because it doesn't have an on-chip pull-up.

interrupt
The W77I058 has a dual-priority interrupt structure with 12 interrupt sources. Each interrupt source has a separate priority bit, flag, interrupt vector and enable bit. Additionally, interrupts can be globally enabled or disabled.
Interrupt Source External interrupts int0 and int1 can be edge-triggered or level-triggered, depending on bits it0 and it1. The ie0 and ie1 bits in the tcon register are the flags to check for generated interrupts. In edge-triggered mode, the intx input is sampled every machine cycle. If the sample is high in one cycle and low in the next cycle, a high-to-low transition is detected and the interrupt request flag iex in tcon or exif is set. Flag bit to request an interrupt. Since external interrupts are sampled every machine cycle, they must remain high or low for at least one full machine cycle. The iex flag is automatically cleared when the service routine is called. If level-sensitive mode is selected, the request source must hold the pin low until the interrupt is serviced. The hardware does not clear the iex flag when entering a service routine. If the interrupt remains low after the service routine completes, the processor can acknowledge another interrupt request from the same source. Watch out for external interrupts
Int2 to Int5 are edge triggered only. By default, the individual interrupt flags corresponding to external interrupts 2 to 5 must be manually cleared by software. It can be configured by hardware clearing by setting the corresponding bit hcx in the t2mod register. For example, if HC2 is set, the hardware will clear the IE2 flag after the program enters the interrupt 2 service routine.
Timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. These flags are set by overflows in timer 0 and timer 1. When the timer interrupt is serviced, the hardware will automatically clear the tf0 and tf1 flags. The timer 2 interrupt is generated by the logical OR (OR) of the tfa and exf2 flags. These flags are set by overflow or capture/reload events in timer 2 operations. The hardware does not clear these flags when the Timer 2 interrupt is executed. Software must resolve the cause of the interrupt between tf2 and exf2 and clear the appropriate flags.
The watchdog timer can be used as a system monitor or as a simple timer. In both cases, the watchdog timer interrupt flag wdif (wdcon.3) will be set when the timeout count is reached. An interrupt will occur if the interrupt is enabled by enable bit eie.4.
Serial blocks can generate interrupts on reception or transmission. The serial block has two interrupt sources, obtained by the ri and ti bits in the scon sfr and the ri and ti bits in the scon1 sfr, respectively. Hardware does not automatically clear these bits, the user must use software to clear these bits.
All interrupt-generating bits can be set or reset by hardware, resulting in a software-initiated interrupt. Each individual interrupt can be enabled or disabled by setting or clearing a bit in ie sfr. IE also has a global enable/disable bit EA which can be cleared to disable all interrupts except PFI at the same time.
Priority Structure Interrupts have three priorities, highest, highest and lowest. Interrupt sources can be individually set high or low. Of course, high-priority interrupts cannot be interrupted by low-priority interrupts. However, there is a predefined hierarchy between the interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests with the same priority. This hierarchy is defined as follows; interrupts are numbered from the highest priority to the lowest.

Timer/Counter 0 and 1
W77I058 has two 16-bit timer/counter. Each timer/counter has two 8-bit registers, forming a 16-bit count register. For timer/counter 0, they are the upper 8-bit register th0 and the lower 8-bit register tl0. Similarly, Timer/Counter 1 has two 8-bit registers th1 and tl1. These two can be configured as timers, counters that count machine cycles, or counters that count external inputs.
When configured as a "timer", the timer counts clock cycles. The timer clock can be programmed to be 1/12 of the system clock or 1/4 of the system clock. In "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in the case of timer 0, and t1 in the case of timer 1. The t0 and t1 inputs are sampled every machine cycle of c4. If the sampled value is high in one machine cycle and low in the next machine cycle, a valid high-low transition on the pin is recognized and the count register is incremented. Since it takes two machine cycles to identify a negative transition on a pin, the maximum rate of counting is 1/24 of the master clock frequency. In "timer" or "counter" mode, the count register will be updated at C3. Thus, in "timer" mode, negative transitions identified on pins t0 and t1 can cause the count register value to be updated only on machine cycles where a negative edge is detected.
The "timer" or "counter" function is selected by the "C/T" bits in the TMOD special function register. Each timer/counter has its own selection bit; bit 2 of tmod selects the function of timer/counter 0, and bit 6 of tmod selects the function of timer/counter 1. Additionally, each timer/counter can be set to operate in any of four possible modes. Mode selection is done by the m0 and m1 bits in the tmod sfr.
Time base selection
The W77I058 provides users with two timer operation modes. The timer can be programmed to work like the standard 8051 series, counting at 1/12 the clock speed. This will ensure that the timing loops on the W77I058 and standard 8051 will match. This is the default operating mode of the W77I058 timer. Users can also choose to count in turbo mode, where the timer will increment at 1/4 clock speed. This will directly triple the counting speed. This selection is done by the tom and t1m bits in the ckcon sfr. A reset sets these bits to 0 and the timer then operates in standard 8051 mode. The user should set these bits to 1 if the timer is to operate in turbo mode.
Mode 0

In Mode 0, the timer/counter acts as an 8-bit counter, with 5 bits divided by 32 prescale. In this mode, we have a 13-bit timer/counter. The 13-bit counter consists of 8-bit thx and 5-bit tlx low-order bits. The upper 3 bits of TLX are ignored.
The negative edge of the clock increments the count in the tlx register. When the fifth bit in TLX moves from 1 to 0, the count in the THX register will increment. When the count in thx moves from ffh to 00h, then the overflow flag tfx in tcon sfr is set. The count input is only available if trx, gate=0 or intx=1 are set. When C/T is set to 0, it will count clock cycles,
If c/t is set to 1, then it will count 1 to 0 transitions for timer 0 and t1 (p3.5) at t0 (p3.4). When the 13-bit count reaches 1ffh, the next count will roll it to 0000h. The timer overflow flag tfx for the associated timer is set and if enabled, an interrupt will occur. Note that when used as a timer, the time base can be clock cycles/12 or clock cycles/4 selected by bit txm of the ckcon sfr.

Mode 1
Mode 1 is similar to Mode 0, except that the count register forms a 16-bit counter instead of a 13-bit counter. This means using all bits of thx and tlx. Rollover occurs when the timer counts from FFFFH to 0000H. The timer overflow flag tfx for the associated timer is set and if enabled, an interrupt will occur. Time base selection in timer mode is similar to mode 0. The operation of the gate function is similar to that in mode 0.
Mode 2
In Mode 2, the timer/counter is in auto-reload mode. In this mode, tlx acts as an 8-bit count register, while thx holds the reload value. When the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the contents of thx, and the counting process continues from there. The reload operation leaves the contents of the thx register unchanged. Counting is enabled by the correct setting of the trx bits and the gate and intx pins. Like the other two modes, 0 and 1 Mode 2 allows counting clock cycles (clock/12 or clock/4) or pulses on pin TN

Mode 3
Mode 3 has different methods of operation for the two timers/counters. For timer/counter 1, mode 3 freezes the counter only. However, Timer/Counter 0 configures TL0 and TH0 as two independent 8-bit count registers in this mode. The logic of this mode is shown in the figure. TL0 uses timer/counter 0
Control bits C/T, gate, TR0, INT0 and TF0. tl0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin t0 determined by c/t (tmod.2). th0 is forced to be used as a clock cycle counter (clock/12 or clock/4) and takes over the use of tr1 and tf1 from timer/counter 1. Mode 3 is used when an additional 8-bit timer is required. While Timer 0 is in Mode 3, Timer 1 can still be used in Modes 0, 1, and 2, but with somewhat limited flexibility. While maintaining its basic functionality, it no longer controls its overflow flag tf1 and enable bit tr1. Timer 1 can still be used as a timer/counter, and the gate and INT1 pins are reserved. In this case, it can be turned on and off by switching it to its own mode 3. It can also be used as a baud rate generator for serial ports.
Timer/Counter 2
Timer/Counter 2 is a 16-bit up/down counter configured by the t2mod register and controlled by the t2con register. Timer/Counter 2 has capture/reload capability. As with the Timer 0 and Timer 1 counters, there is considerable flexibility in selecting and controlling the clock and in defining the mode of operation. The clock source for Timer/Counter 2 can be selected for the external t2 pin (c/t2 = 1) or the crystal oscillator, which is divided by 12 or 4 (c/t2 = 0). The clock is enabled when tr2 is 1 and disabled when tr2 is 0.

Capture mode is achieved by setting the cp rl/2 bit in the t2con register to 1, the rclk and the tclk bit must be cleared. In capture mode, Timer/Counter 2 operates as a 16-bit up-counter. When the counter rolls back from ffffh to 0000h, the t2 bit will be set, which will generate an interrupt request. If the exen2 bit is set, a negative transition of the t2ex pin will cause the rcap2l and rcap2h registers to capture the value in the tl2 and th2 registers. This operation also causes the exf2 bit in t2con to be set, which will also generate an interrupt. By setting the t2cr bit (t2mod.3), the w77i058 allows hardware to automatically reset Timer 2 after capturing the values of tl2 and th2.
Auto-reload mode, counts up by clearing the cp rl/2 bit in the t2con register, enabling auto-reload mode as an incrementing counter. The rclk and tclk bits must be cleared, and the dcen bit in the t2mod register must be cleared. In this mode, Timer/Counter 2 is a 16-bit up-counter. When the counter rolls over from ffffh, a reload occurs, causing the contents of the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. The reload operation also sets the tf bit. Negative transitions of the T2EX pin will also cause a reload if the exen2 bit is set. This operation also sets the exf2 bit in t2con.

Auto-reload mode, count up/down If the cp rl/2 bit in t2con is cleared, timer/counter 2 will be in auto-reload mode as an up/down counter. The rclk and tclk bits must be cleared, and the dcen bit in t2mod must be set. In this mode, Timer/Counter 2 is an up/down counter whose direction is controlled by the t2ex pin. A 1 on the pin makes the counter count. Overflow while counting will cause the counter to be reloaded with the contents of the capture register. With the contents of the timer/counter equal to the capture register, the next countdown will load ffffh into timer/counter 2. In either case, a reload will set the tfa bit. Reloading will also toggle the exf2 bit. However, in this mode, the exf2 bit cannot generate interrupts.
Baud Rate Generator Mode The baud rate generator mode is enabled by setting the rclk or tclk bits in the t2con register. In Baud Rate Generator mode, Timer/Counter 2 is a 16-bit counter that automatically reloads when the count rolls over from ffffh. However, rolling-over does not set the tf bit. If the exen2 bit is set, a negative transition of the t2ex pin will set the exf2 bit in the t2con register and cause an interrupt request. In this mode, the t2oE bit must be cleared.

Programmable Clock Out Timer 2 is equipped with a new clock out feature that outputs a 50% duty cycle clock on P1.0. It can be called as a programmable clock generator. To configure Timer 2 for clock output mode, software must start Timer 2 by setting bits t2oe=1, c/t2=0, and cp/rl=0. Setting bit tr2 will start the timer. This mode is similar to the Baud Rate Generator mode in that it does not generate an interrupt when Timer 2 overflows. Therefore, Timer 2 can be used as baud rate generator and clock generator at the same time. The punch frequency is determined by the following formula:
clock output frequency = oscillator frequency / [4 x (65536-RCAP2H, RCAP2L)]
Watchdog Timer The watchdog timer is a free-running timer that the user can program as a system monitor, time base generator, or event timer. It's basically a set of dividers that divide the system clock. The divider output selects and determines the time-out interval. When a timeout occurs, a flag is set, which may cause an interrupt if enabled, or a system reset if enabled. Interrupts will occur if separate interrupt enable and global enable are set. The interrupt and reset functions are independent of each other and can be used individually or together according to user software.
The watchdog timer should first be restarted using rwt. This ensures that the timer starts from a known state. The rwt bit is used to restart the watchdog timer. This bit is self-clearing, that is, software will automatically clear this bit after writing a 1 to this bit. The watchdog timer will now count clock cycles. The timeout interval is selected by the two bits wd1 and wd0 (ckcon.7 and ckcon.6). When the selected timeout occurs, the watchdog interrupt flag wdif (wdcon.3) will be set. After the timeout occurs, the watchdog timer will wait an additional 512 clock cycles. If the watchdog reset EWT (WDCON.1) is enabled, 512 clocks after the timeout, if there is no RWT, a system reset due to the watchdog timer will occur. This will last for two machine cycles and will set the watchdog timer reset flag wtrf (wdcon.2). This indicates to the software that the monitor is the cause of the reset.
When used as a simple timer, reset and interrupt functions are disabled. The timer will set the WDIF flag whenever the timer completes the selected interval. The wdif flag is polled to detect timeouts, and rwt allows software to restart the timer. The watchdog timer can also be used as a very long timer. In this case, the interrupt function is enabled. Every time a timeout occurs, an interrupt will occur if the global interrupt enable EA is set.
The watchdog timer is mainly used as a system monitor. This is very important in real-time control applications. Under certain power failure or electromagnetic interference conditions, the processor may begin executing erroneous code. If this option is not checked, the entire system may crash. Using the watchdog timer interrupt during software development will allow the user to select the ideal watchdog reset location. The code is first written without a watchdog interrupt or reset. Then, the watchdog interrupt is enabled to identify the code location where the interrupt occurred. Users can now insert instructions to reset the watchdog timer, which will allow code to run without any watchdog timer interrupts. Now that the watchdog timer reset is enabled, the watchdog interrupt may be disabled. If any error code is executed now, the reset watchdog timer instruction will not execute at the desired instant and a watchdog reset will occur.
The watchdog timeout selection will result in different timeout values depending on the clock speed.
When enabled, the reset will occur 512 clocks after the timeout occurs.

serial port
The serial port in the W77I058 is a full duplex port. The W77I058 provides users with additional functions such as framing error detection and automatic address recognition. The serial port is capable of synchronous and asynchronous communication. In synchronous mode, the W77I058 generates the clock and operates in half-duplex mode. In asynchronous mode, full-duplex operation is available. This means it can send and receive data at the same time. Both transmit registers and receive buffers are programmed as sbuf special function registers. However, any write to sbuf will write to the transmit register, while reads to sbuf will be done from the receive buffer register. The serial port can operate in four different modes, described below.
Mode 0

This mode provides synchronous communication with external devices. In this mode, serial data is sent and received on the rxd line. TXD is used to transmit the shift clock. Whether the device is sending or receiving, the w77i058 provides the txd clock. Therefore, this mode is a half-duplex serial communication mode. In this mode, 8 bits are sent or received per frame. First send/receive lsb. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This baud rate is determined by the sm2 bit (scon.5). When this bit is set to 0, the serial port runs at 1/12 the clock. When set to 1, the serial port runs at 1/4 of the clock. The extra feature of programmable baud rate in Mode 0 is the only difference between the standard 8051 and the W77I058.
The functional block diagram is shown below. Data goes in and out of the serial port on the rxd line. The TXD line is used to output the shift clock. The shift clock is used to shift data in and out of the W77I058 and the device on the other end of the line. Any instruction that causes a write to sbuf will initiate a transfer. The shift clock will be activated and the data will be shifted on the RXD pin until all 8 bits have been transmitted. If sm2=1, the data on rxd will appear 1 clock cycle before the falling edge of the shift clock on txd. Then the clock on TXD stays low for two clock cycles and then goes high again. If sm2=0, the data on rxd will appear 3 clock cycles before the falling edge of the shift clock on txd. Then the clock on TXD stays low for 6 clock cycles and then goes high again. This ensures that on the receiving end, data on the rxd line can be clocked on the rising edge of the shift clock on txd, or locked when the txd clock is low.

Mode 1

In Mode 1, full-duplex asynchronous mode is used. A serial communication frame consists of 10 bits transmitted on txd and received on rxd. The 10 bits consist of a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SFR SCON. The baud rate in this mode is variable. The serial baud rate can be programmed to 1/16 or 1/32 of Timer 1 overflow. Since Timer 1 can be set to different reload values, the baud rate can vary widely.
The transfer starts with writing to sbuf. After the first rollover of the divide-by-16 counter, the serial data is brought onto the TXD pin at C1. Following the next rollover of the divide-by-16 counter, the next bit is placed on the txd pin at c1. Therefore, the transfer is synchronized with the divide-by-16 counter, not directly with the write sbuf signal. After all 8 bits of data have been sent, the stop bit is sent. After the stop bit is output on the TXD pin, the TI flag is set in the C1 state. This will be the 10th roll of the counter divided by 16 after writing to sbuf.
Reception is enabled only when ren is high. The serial port actually starts receiving serial data, a falling edge is detected on the RXD pin. A 1-to-0 detector continuously monitors the RXD line, sampling at 16 times the selected baud rate. When a falling edge is detected, the divide-by-16 counter is reset immediately. This helps align bit boundaries with rollovers of the divide-by-16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. Bit detection is done on a best of three basis. The bit detector samples the rxd pin at the 8th, 9th and 10th counter states. Bit values are selected by using a 3-to-2 majority voting system. This is done to improve the noise rejection characteristics of the serial port. If the first bit detected after the falling edge of the rxd pin is not 0, this indicates that the start bit is invalid and the reception is aborted immediately. The serial port again looks for a falling edge in the rxd line. If a valid start bit is detected, the remaining bits are also detected and shifted into sbuf.
After shifting in 8 data bits, there is one more shift to do, after which sbuf and rb8 are loaded and ri is set. However, before ri can be loaded and set, certain conditions must be met.
1. ri must be 0 and
2. sm2=0 or received stop bit=1.
If these conditions are met, the stop bit goes to rb8, the 8 data bits go to sbuf and ri is set. Otherwise received frames may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1 to 0 transition on the RXD pin.

The security bit is in the on-chip rom operating mode, and the flash-eprom can be repeatedly programmed and verified. Before confirming that the code in the rom is normal, the code can be protected. The protection of the rom and its operation are described below.
The W77I058 has several special setup registers, including security registers, which cannot be accessed in normal mode. These registers can only be accessed from the rom operating mode. Once the bits of the security register are programmed from high to low, they cannot be changed. They can only be reset by an erase all operation. The security registers are addressed at address 0ffffh in rom operating mode.

B0: Lock bit This bit is used to protect the client program code in W77I058. It can be set after the programmer has finished programming and verified the sequence. Once this bit is set to logic 0, the rom data and special setup registers cannot be accessed again.
B1:MOVC Inhibit This bit is used to limit the accessible area of the MOVC instruction. It prevents movc instructions in external program memory from reading internal program code. When this bit is set to logic 0, MOVC instructions in the external program memory space will only be able to access code in external memory, not code in internal memory. A movc instruction in the internal program memory space will always be able to access rom data in both internal and external memory. If this bit is logic 1, there is no restriction on the MOVC instruction.