General Instructions

The AD7863 is a high speed, low power, dual 14-bit analog-to-digital converter that operates from a 5 volt supply. This section includes two 5.2µs successive approximation ADCs, two track/hold amplifiers, an internal 2.5v reference, and a high-speed parallel interface. The four analog inputs are divided into two channels (A and B), selected by the a0 input. Each channel has two inputs (v and v or v and v) that can be sampled and converted simultaneously, preserving the relative phase information of the signal at the two analog inputs. The part accepts analog input ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage. A1A2 B1 B2 A single conversion start signal (convst) puts both tracks/holds on hold simultaneously and initiates conversions on both channels. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The transformed first read accesses the result from v or v, and the second read accesses the result from v or v, depending on whether the mux selection (a0) is low or high, respectively. The data is read from the part through a 14-bit parallel data bus. A1 B1 A2 B2 has standard CS and RD signals. In addition to traditional DC accuracy metrics such as linearity, gain, and offset error, this section specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

The AD7863 is fabricated on Analog Devices' Linear Compatible CMOS (LCMOS) process, a hybrid technology2 process that combines precision bipolar circuitry with low-power CMOS logic. Available in 28 lead SOIC W and SSOP.

Product Highlights

1. The AD7863 has two complete ADC functions, allowing simultaneous sampling and conversion of two channels. Each adc has a dual channel input mux. After the conversion is started, the conversion result for both channels is 5.2 μs.

2. The AD7863 is powered by a 5 volt power supply and typically consumes 70 megawatts. Automatic power-off mode, the components are powered off once

A conversion completes and wakes up before the next conversion cycle, making the AD7863 ideal for battery-powered or portable applications.

3. This part provides a high-speed parallel interface for easy connection with microprocessors, microcontrollers and digital signal processors.

4. There are three versions of this part with different analog input ranges. AD7863-10 provides standard industrial

The input range is ±10 V; the AD7863-3 provides a common signal processing input range of ±2.5 V, while the AD7863-2 can be used in unipolar 0 V to 2.5 V applications.

5. This section features very tight aperture delay matching between the two input sample-and-hold amplifiers.

Converter Details

The AD7863 is a high speed, low power, dual 14-bit analog-to-digital converter that operates from a 5 volt supply. This section contains two 5.2µs successive approximation ADCs, two track-and-hold amplifiers, an internal 2.5v reference, and a high-speed parallel interface. The four analog inputs are divided into two channels (A and B), selected by the a0 input. Each channel has two inputs (v and v or v and v) that can be sampled and converted simultaneously, preserving the relative phase information of the signals at the two analog inputs. The part accepts analog input ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage. AD7863 has two working modes, high sampling mode and automatic sleep mode. After the conversion is completed, the part automatically enters the sleep state. These modes are discussed in detail in the Timing and Control section. A1A2 basement one basement two basement, on AD7863 through the pulse converter to start the conversion input. On the falling edge of convst, the on-chip track and hold are simultaneously placed in hold and a conversion sequence is initiated on both channels. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The first read after conversion accesses the result from v or v, and the second read accesses the result from v or v, depending on whether the multiplexer selects a0 low or high, respectively, before starting the conversion. Read data from parts through 14 bits A1 B1 A2 B2, parallel data bus with standard CS and RD signals.

In high sampling mode, the AD7863 has a conversion time of 5.2 μs (10 μs in auto-sleep mode) and a track/hold acquisition time of 0.5 μs. For best performance from the part, read operations should not be performed during a conversion or during the 400 ns period before the next conversion. This allows the part to operate at throughputs up to 175 kHz and meet data sheet specifications.

track holding section

The track-and-hold amplifier on the AD7863 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track and hold is greater than the Nyquist rate of the ADC, even though the ADC is operating at its maximum throughput rate of 175 kHz (ie, the track and hold can handle input frequencies in excess of 87.5 kHz).

The track-and-hold amplifier acquires an input signal with 14-bit precision in less than 500ns. The operation of tracks and holds is basically transparent to the user. The dual rail and hold amplifiers simultaneously sample their respective input channels, on the edge of the constellation. The orbit and hold aperture times (i.e. the external convst signal versus the orbit and hold that actually goes into hold) are well matched on both tracks, held on one device, and well matched between devices. This allows relative phase information between different input channels to be accurately preserved. It also allows multiple ad7863s to sample more than two channels simultaneously. At the end of the conversion, the part returns to its tracking mode. The acquisition time of the track and hold amplifier starts at this point.

Reference chapter

The AD7863 includes a reference pin labeled V, which provides access to the part's own 2.5 V reference. Alternatively, an external 2.5 V reference can be connected to this pin to provide a reference voltage source for the part. This part is specified for a 2.5 V reference voltage. Errors in the reference source cause gain errors in the AD7863 transfer function and add to the full-scale errors specified on the part. On the AD7863-10 and AD7863-3, it also causes offset errors to be injected in the attenuator stage. referee

The AD7863 contains an on-chip 2.5 volt reference. To use this reference as a reference source for the AD7863, connect two 0.1µf disc ceramic capacitors from the V pin to the AgNd. The voltage at this pin appears in the ref

is being applied to ADC. If the reference needs to be used external to the AD7863, it should be buffered because the part has a FET switch in series with the reference output, resulting in a source impedance of 5.5 kΩ (nominal) for this output. At 25°C, the internal reference has a tolerance of ±10 mV, a typical temperature coefficient of 25 ppm/°C, and a maximum temperature error of ±25 mV.

If the application requires a reference with tighter tolerances or the AD7863 needs to be used with a system reference, the user can choose to connect an external reference to this V pin. The external reference effectively overdraws the internal reference, thus providing a reference source for the ADC. The reference input is buffered before being applied to the ADC with a maximum input current of ±100µA. A suitable reference for the AD7863 is the AD780 precision 2.5 V reference.

Circuit Description

Analog input section

The AD7863 is divided into three types: AD7863-10 (handling a ±10 V input voltage range), AD7863-3 (handling a ±2.5 V input voltage range), and AD7863-2 (handling a 0 V to 2.5 V input voltage range). Figure 5 shows the analog input section of the AD7863-10 and AD7863-3. The analog input range of the AD7863-10 is ±10 V, and the input resistance is typically 9 kΩ. The analog input range of the AD7863-3 is ±2.5 V, and the input resistance is typically 3 kΩ. This input is benign, with no dynamic charging current, because the resistive stage is followed by the rail-holding amplifier's high input impedance stage. For the AD7863-10, r1=8 kΩ, r2=2 kΩ, and r3=2 kΩ. For AD7863-3, r1=r2=2 kΩ, r3 is open.

Offset and full scale adjustment

In most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. With AC coupling, offset errors in the analog domain can be eliminated. The full-scale error effect is linear and should not cause a problem as long as the input signal is within the full dynamic range of the ADC. Some applications always require the input signal to span the entire analog input dynamic range. In this application, the offset and full-scale errors must be adjusted to zero.

Figure 6 shows a typical circuit that can be used to adjust the offset and full-scale error on the AD7863 (V shown on the AD7863-10 version is for example purposes only). When adjustment is required, the offset error must be adjusted before the full-scale error. This is accomplished by fine-tuning the offset of the op amp driving the AD7863's analog input when the input voltage is below 1/2 LSB of analog ground. The trimming procedure is as follows: Apply a voltage of -0.61 mV (-1/2 lsb) at V in Figure 6 and adjust the opamp offset voltage until the ADC output code is between 11 1111 1111 1111 and 00 0000 0000 0000 0000 flashes between.

Gain error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure in both cases is as follows:

Positive full-scale adjustment (-10 type)

A voltage of 9.9927 V (fs/2–1 lsbs) was applied at V. Adjust R2 until the ADC output code flashes between 01 1111 1111 1110 and 01 1111 1111 1111.

Negative full scale adjustment (-10 model)

A voltage of -9.9976 V (-fs + 1 lsb) was applied at V. Adjust R2 until the ADC output code flashes between 10 0000 0000 0000 and 10 0000 0000 0001.

An alternative to adjusting the full-scale error in systems using an external reference is to adjust the voltage at the v pin until the full-scale error is adjusted for any channel. Good full-scale matching of the channels ensures small full-scale errors for other channels.

time and control

Figure 7 shows the timing and control sequence required to obtain optimum performance (Mode 1) from the AD7863. In the sequence shown, starting a conversion on the falling edge of the first puts both the track and hold into hold, and new data from this conversion is available in the output register of the AD7863 in the following 5.2µs. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. Then start the second conversion. If the multiplexer select (a0) is low, the first converted first and second read pulses access the results from channel a (v and v, respectively). After the second transition and a0 high, the third and fourth read pulses access the results from channel b (v and v respectively). The state of a0 can be made high in A1A2 B1 B2 convst, that is, tracked and held at hold and 500 ns. before the next falling edge of the convs. Note that during a conversion, if a negative voltage is applied to a non-selected channel (not within the input range of the AD7863), then a0 should not be changed as this will affect the conversion in progress. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals, i.e. a read operation is performed by a negative going pulse on the CS pin and two negative going pulses on the rd pin (when cs is low ), accessing two 14-bit results. Once a read has taken place, another 400 ns should be allowed before the next read. The falling edge of convst optimizes the track and holds the amplifier settings before the next conversion begins. The achievable throughput of the part is 5.2 μs (conversion time) plus 100 ns (read time) plus 0.4 μs (quiet time). This results in a minimum throughput time of 5.7µs (equivalent to a throughput rate of 175khz).

In addition to the read operations previously described and shown, other cs and rd combinations in Figure 7 can result in different channels/inputs being read in different combinations. Appropriate combinations are shown in Figures 8, 9 and 10.

Operating mode

Mode 1 operation: normal power, high sampling performance

The timing diagram in Figure 7 is for optimum performance in operating mode 1, where the falling edge of convst initiates the transition and puts the rail and hold amplifier into their hold mode. This falling edge of convst also causes the busy signal to go high to indicate that a conversion is in progress. When the conversion is complete, the busy tone signal goes low for a maximum of 5.2µs after the falling edge of convst, and new data from this conversion is available in the output latch of the AD7863. Read operations access this data. If the multiplexer select a0 is low, the first converted first and second read pulses access the results from channel a (v and v, respectively). After the second transition and a0 high, the third and fourth read pulses access the results from channel b (v and v, respectively). Read data from parts through 14 bits A1A2 B1 B2, parallel data bus with standard CS and RD signals. This data read operation consists of a negative-going pulse on the CS pin and two negative-going pulses on the RD pin (while CS is low), accessing two 14-bit results. For the fastest throughput, read operations take 100 nanoseconds. The read operation must complete at least 400 ns before the fall. The edge of the next convst, which will give a total time of 5.7 μs for the entire throughput time (equivalent to 175 kHz). This mode of operation should be used for high sampling applications.

Mode 2 operation

Shut down, automatically hibernate after conversion

The timing diagram in Figure 11 is for optimum performance in operating mode 2. After a conversion, once the busy signal goes low, the part automatically enters sleep mode and wakes up before the next conversion occurs. This is done by keeping convst low at the end of the second conversion and convst high at the end of the second conversion for mode 1 operation.

The operation shown in Figure 11 shows how to access data from channel A and channel B, followed by auto-sleep mode. It is also possible to set the timing so that data is only accessed from either channel A or channel B (see the "Read Options" section) and then enter auto-sleep mode. The rising edge of Const awakens the character. When using the external reference, the wake-up time is 4.8 µs, and when using the internal reference, the wake-up time is 5 ms, at which point the track and hold amplifiers enter their hold mode as long as convst goes low. After this, the conversion takes 5.2µs, a total of 10µs from the rising edge (external reference, 5.005ms for the internal reference) from convst to the completion of the conversion, which is indicated by busy going low.

Note that because the wake-up time from the rising edge of convst is 4.8 μs, if the convst pulse width is greater than 5.2 μs, the conversion time is greater than 10 μs as shown in Figure 11 (4.8 μs wake-up time + 5.2 μs conversion time). Const rising edge. This is because the track and hold amplifiers in convst and transitions can no longer last 5.2µs. In this case, being busy is the best indicator that the conversion is complete. Data can be read from the component even when the component is in sleep mode.

The read operation is the same as in Mode 1 and must be allowed enough time for the track and hold amplifier to resolve after a transition. This mode is useful when the part is transitioning at low speed because the power consumption is significantly lower than that of Mode 1 operation.

Dynamic Specifications

The AD7863 specifies and tests dynamic performance and traditional dc specifications such as integral and differential nonlinearity. These AC specifications are required for signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the AD7863 include snr, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in detail in the following sections.

signal to noise ratio

snr is the signal-to-noise ratio measured at the ADC output. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding dc, and has a maximum value of half the sampling frequency (f/2); the signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels , the smaller the quantization noise. The theoretical signal-to-noise ratio of a sine wave input is given by S

SNR=(6.02N+1.76)dB(1)

where n is the number of digits. So, for an ideal 14-bit converter, the signal-to-noise ratio is 86.04db.

Figure 12 shows the histogram of 8192 dc input conversions with the AD7863 using a 5 V supply. The analog input is set at the center of the transcoding. It can be seen that the codes appear mostly in one output bin, which shows that the ADC has very good noise performance.

The output spectrum of the ADC is evaluated by applying a very low distortion sine wave signal to the V input, which is sampled at 175 kHz. Generates a Fast Fourier Transform (fft) plot from which SNR data can be obtained. Figure 13 shows a typical 8192-point FFT plot of the AD7863 with an input signal of 10 kHz and a sampling frequency of 175 kHz. The signal-to-noise ratio obtained from this figure is -80.72db. Harmonics should be considered when calculating the signal-to-noise ratio.

significant digits

The formula given in Equation 1 relates the signal-to-noise ratio to the number of bits. Rewriting the formula, as in Equation 2, can obtain a performance metric expressed in effective number of bits (n).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio.

Figure 14 shows a typical plot of effective bits versus frequency for the AD7863-2 sampled at 175 kHz. The effective number of bits is typically between 13.11 and 11.05, corresponding to SNR figures of 80.68db and 68.28db.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (thd) is the ratio of the rms value of the harmonics to the rms value of the fundamental. For the AD7863, THD is defined as

where:

V1 is the rms amplitude of the fundamental wave.

V2, v, v and v are the rms amplitudes of the second to fifth harmonics. The 345thd is also derived from the fft plot of the adc output spectrum.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity produces distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3. …Intermodulation terms are those where neither m nor n equals zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs. In this case, the input consists of two equal-amplitude, low-distortion sine waves. Figure 15 shows a typical IMD diagram for the AD7863.

Peak harmonics or spurious noise

Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to f/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for parts of the harmonic buried in the noise floor, the peak is the noise peak.

DC Linear Graph

Figure 16 and Figure 17 show typical DNL and INL plots for the AD7863.

Power Factor

In auto power-down mode, the part can operate at sample rates well below 175 kHz. In this case the power consumption is reduced and depends on the sampling rate. Figure 18 shows a graph of power consumption versus sampling rate from 1 Hz to 100 kHz in auto power-down mode. Condition is 5 V supply at 25°C.

Microprocessor interface

The AD7863 high-speed bus timing allows direct connection to DSP processors as well as modern 16-bit microprocessors. Suitable microprocessor interfaces are shown in Figures 19 to 23.

AD7863 to ADSP-2100 interface, Figure 19 shows the AD7863 and ADSP-2100. The convst signal can be provided by the adsp-2100 or an external power supply. The AD7863 is busy providing an interrupt to the adsp-2100 when the conversion is done on both channels. These two conversion results can then be read from the ad7863 using two consecutive reads to the same memory address. The following instruction reads one of two results: mr0=dm (analog-to-digital converter)

Where: MR0 is the ADSP-2100 MR0 register; ADC is the AD7863 address.

AD7863 to ADSP-2101/ADSP-2102 Interface

The interface outlined in Figure 19 also forms the basis for the interface between the AD7863 and the ADSP-2101/ADSP-2102. The read line of the ADSP-2101/ADSP-2102 is marked rd.in, this interface, the rd pulse width of the processor can be programmed using the data memory wait state control register. The instructions for reading one of the two results are as described in the adsp-2100.

AD7863 to TMS32010 Interface, showing the interface between the AD7863 and the tms32010. in Figure 20. Again, the convst signal can be provided from the tms32010 or an external source, and the tms32010 is interrupted when both conversions are complete. The following instructions are used to read the conversion result from the AD7863: In D, ADC

Where: D is the data memory address; ADC is the AD7863 address.

AD7863 to TMS320C25 interface

Figure 21 shows the interface between the AD7863 and the tms320c25. As with the previous two interfaces, conversions can be initiated from the tms320c25 or an external source, and the processor is interrupted when the conversion sequence is complete. The tms320c25 does not have a separate rd output to directly drive the ad7863rd input. This has to be generated by the processor strb and r/w output, with some logic gates added. The RD signal is or is gated with the msc signal to provide a wait state during the read cycle required for correct interface timing. Read the conversion result from the AD7863 using: in D, ADC

Where: D is the data memory address; ADC is the AD7863 address.

AD7863 to MC68000 interface

The interface between the AD7863 and the MC68000 is shown in Figure 22. As before, conversions can be provided from the MC68000 or from an external source. The AD7863 busy can be used to interrupt the processor, or a software delay can ensure that the conversion has completed before attempting to read the AD7863. Due to its interrupted nature, the MC68000 requires additional logic (not shown in Figure 23) to allow it to be interrupted properly.

The MC68000 AS and R/W outputs are used to generate the RD input signal of the split AD7863. CS is used to drive the MC68000 packet input to allow the processor to perform normal read operations on the AD7863. Use the following MC68000 instructions to read the conversion result: move adc, d0

Where: D0 is the 68000 D0 register; the ADC is the AD7863 address.

AD7863 to 80C196 interface

Figure 23 shows the interface between the AD7863 and the 80C196 microprocessor. Here, the microprocessor initiates the conversion. This is achieved by gating the 80c196wr signal with the decoded address output (different from the ad7863 cs address). The AD7863 busy is used to interrupt the microprocessor when the conversion sequence is complete.

Vector Motor Control

The electric current of the motor can be divided into two parts: one part produces the torque, and the other part produces the magnetic flux. For optimum motor performance, these two components should be controlled independently. In traditional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the fundamental control variables. However, both torque and magnetic flux are functions of current (or voltage) and frequency. This coupling effect can degrade the performance of the motor because, for example, if the torque is increased by increasing the frequency, the magnetic flux tends to decrease.

Vector control of an AC motor involves controlling the phase in addition to the drive and current frequency. Controlling the phase of the motor requires feedback from the position of the rotor relative to the rotating magnetic field within the motor. Using this information, the vector controller mathematically converts the three-phase drive currents into individual torque and flux components. The AD7863 is ideal for vector motor control applications.

A block diagram of a vector motor control application using the AD7863 is shown in Figure 24. The position of the magnetic field is determined by determining the current in each phase of the motor. Only two phase currents need to be measured, because if two phases are known, a third current can be calculated. V and V of the AD7863 are used to digitize this information. A1A2

Simultaneous sampling is essential to maintain relative phase information between the two channels. A current-sensing isolation amplifier, transformer, or Hall-effect sensor is used between the motor and the AD7863. The rotor information is obtained by measuring the voltages at the two inputs of the motor. V and V of the AD7863 are used to obtain this information. The relative phase of the two channels is equally important. Use dsp microprocessor to carry out mathematical transformation and control loop calculation to the information fed back by ad7863. There are multiple AD7863S on the first basement and the second basement.

Figure 25 shows a system in which multiple AD7863s can be configured to handle multiple input channels. This configuration is common in applications such as sonar and radar. The AD7863 has typical aperture delay limitations. This means that the user knows the difference in sampling instants between all channels. The common read signal from the microprocessor drives the RD input of all AD7863s. Each AD7863 is assigned a unique address selected by the address decoder. The reference output of AD7863 #1 is used to drive the reference inputs of all other AD7863s in the circuit shown in Figure 25. A V can be used to provide a reference to several other AD7863S. Alternatively, an external or system reference can be used to drive all V inputs. A common reference ensures good full-scale tracking between all channels.

Application Tip: PC Board Layout Considerations

The AD7863 is optimized to achieve the lowest noise performance in terms of both radiated and conducted noise. To complement the AD7863's excellent noise performance, great care must be taken with the PC board layout. Figure 26 shows the recommended connection diagram for the AD7863.

horizon

The AD7863 and associated analog circuitry should have a separate ground plane, called the analog ground plane (AGND). This analog ground plane should include all AD7863 ground pins (including the DGND pin), voltage reference circuits, power supply bypass circuits, analog input traces, and any associated input/buffer amplifiers. The regular PCB ground plane (called dgnd in this discussion) area should contain all digital signal traces (excluding ground pins) up to the AD7863.

powered aircraft

The PC board layout should have two different power planes, one for the analog circuits and one for the digital circuits. The analog power plane should include the AD7863 (V) and all associated analog circuitry. If necessary, as shown in Figure 26, this power plane should be connected to a regular PCB power plane (V) at a single point via a ferrite bead. This bead (reference part number: DD Cocos Fair Rite 274300111 or Murata BL01/02/03) should be within three inches of the AD7863.

The PCB power plane (V) should provide power to all digital logic on the PC board, while the analog power plane (V) should provide power to all AD7863 power pins, voltage reference circuits, and any input amplifiers (if required). A suitable LNA for the AD7863 is the AD797, one for each input. Make sure that the +V and -V supplies of each amplifier are disconnected from AGND, respectively. Cocos DDSS, PCB power (V) and ground (DGND) should not cover parts of the analog power plane (V). Keeping v power and dgnd planes not covering v helps reduce plane-to-plane noise coupling.

Power decoupling

Noise on the analog power plane (V) can be further reduced by using multiple decoupling capacitors, with disc ceramic capacitors for best performance. The V and reference pins (whether using an external or internal reference) should be separated from the analog ground plane (AGND) individually. This should be accomplished by placing the capacitors as close as possible to the pins of the AD7863, keeping the capacitor leads as short as possible to minimize lead inductance.