feature

333K samples/sec; standard ±10V and ±5V input ranges;

DC performance over temperature: no missing code 1/2LSB integral linearity error 3/4LSB differential linearity error;

AC performance over temperature: 72db signal-to-noise ratio 80db spurious free dynamic range -80db total harmonic distortion Internal sample/hold, reference, clock and tri-state output Power consumption: 215mw Maximum package: 24-pin single wide tilt.

24-lead SOIC

describe

The ADS7800 is a complete 12-bit sampling analog-to-digital converter using state-of-the-art CMOS architecture. It contains a complete 12-bit successive approximation A/D converter with internal sample/hold, reference, clock, microprocessor controlled digital interface and tri-state output drivers.

The ADS7800 is specified for a 333kHz sampling rate. Conversion times are factory set to 2.70 microseconds maximum temperature, and the high-speed sampling input stage ensures a total acquisition and conversion time of 3 microseconds maximum temperature. Precision laser trimmed scaling resistors provide industry standard input ranges of ±5V or ±10V.

AC and DC performance are fully specified. Two grades based on linear and dynamic performance provide the best price/performance for a wide range of applications.

The 24-pin ADS7800 is available in plastic and side solder hermetically sealed 0.3" wide dips, and in SOIC packages. It is powered by a +5V supply and a -12V or -15V supply. The ADS7800 has a temperature range of 0°C to +70°C and -40 Between °C and +85°C.

theory of operation

The AD7800 combines the advantages of advanced CMOS technology (logic density, stable capacitors and good analog switches) with Burr Brown's proven technology in laser edge thin film resistors to provide a complete sampling A/D converter.

A basic charge redistribution successive approximation structure converts the analog input voltage into a digital word. Figure 1 shows the operation of a simplified 3-bit charge redistribution A/D. Precision laser-trimmed scaling resistors at the input divide the standard input range (±10V or ±5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array.

In sample mode, the capacitor array switch of the msb capacitor (s1) is in the "s" position so that the charge on the msb capacitor is proportional to the voltage level of the analog input signal, and the remaining array switches (s2 and s3) are set to "s" r" position to provide an accurate bipolar offset EF from the reference source r. At the same time, the switch sc is also in the off position to automatically zero out any offset error in the cmos comparator.

When a convert command is received, switch s1 opens to capture the charge on the msb capacitor proportional to the input level at the time of the sampling command, switches s2 and s3 open to capture the offset charge, and switch sc opens to float the comparator input. By connecting switches s1, s2 and s3 to position "r" (connected to ref) or "g" (connected to gnd) in sequence, changing the voltage developed at the input node of the comparator, the charge trapped on the capacitor array can now be move between the three capacitors in the .

The first approximation connects the msb capacitor to ref through switch s1, while switches s2 and s3 connect to gnd. Depending on whether the comparator output is high or low, the logic will then lock s1 in the "r" or "g" position and make the next approximation by connecting s2 to ref and s3 to gnd. When doing three consecutive approximation steps for this simple converter, the voltage level of the comparator will be within 1/2lsb of gnd and the data output word will be based on where s1, s2 and s3 are read.

operate

Basic operation

Figure 2 shows the simple connection circuit required to operate the ADS7800 over a ±10V range in conversion mode. A conversion command arrives at pin 19, R/C, (pulse acquisition pin 19 low for at least 40ns) will hold the ADS7800 in mode and start conversion. During a conversion, pin 21 busy will remain low and will only rise after the conversion is complete and data has been transferred to the output latch. Therefore, the rising edge of the signal on pin 21 is available for slave transitions. In addition, during conversion, the busy signal puts the output data lines into a hi-z state and inhibits the input lines. This means that pulses on pin 19 are ignored, so new conversions cannot be initiated during conversions, either due to spurious signals or to shorten the period of the ADS7800. In read mode, the input to pin 19 is held normally low and a high pulse is used to read the data and initiate a conversion. In this mode, a rising edge of R/C on pin 19 will enable the output data pin and the data from the previous conversion will become valid. The falling edge then puts the ADS7800 into holdover mode and initiates a new conversion. The ads7800 will start taking new samples as soon as the conversion is complete, even before the busy output on pin 21 rises, and will track the input signal until the next conversion starts, whether in conversion mode or read mode. When used with an 8-bit bus, data can be read out in two bytes under the control of pin 18HBE. With a low input at pin 18, at the end of the conversion, the 8 lsb's of data are loaded into the latches at pins 9 to 12 and 14 to 17. Turn pin 18 high, then load 4 msb on pins 14 to 17 and force pins 9 to 12 low.

Analog input range

The ADS7800 provides two standard bipolar input ranges: ? 0V and ? 5V. If needed? 0V range, the analog input signal should be connected to pin 1. Signals requiring a ±5V range should be connected to pin 2. In either case, the other of these two pins must be grounded or connected to the trim circuit described in the Calibration section.

Controlling the ADS7800

The ADS7800 can be easily interfaced to most microprocessor-based systems and other digital systems. The microprocessor can fully control each conversion, or the ADS7800 can operate in stand-alone mode with only input and output. Full control includes initiating conversions and reading output data at user command, transferring all 12-bit data in one parallel word, or transferring data bytes in two 8-bits. The three control inputs (CS, R/C and HBE) are all TTL/CMOS compatible.

For stand-alone operation, control of the ADS7800 is accomplished by a single control line connected to R/C.in. In this mode, CS and HBE are connected to GND. The output data is displayed as a 12-bit word. Standalone mode is used in systems that contain dedicated input ports that do not require full bus interface functionality. A transition is initiated by a high-to-low transition on R/C. High when R/C is high and busy. Therefore, there are two possible modes of operation: the conversion can be initiated with a positive or negative pulse. In both cases, the R/C pulse must be kept for a minimum of 40ns. Figure 6 illustrates the timing when a conversion is initiated by the R/C pulse, which goes low and returns high during the conversion. In this case (conversion mode), the tri-stated output goes into the hi-z state in response to a falling edge and enables external access to the data after the conversion is complete.

Figure 7 illustrates the timing to initiate a conversion, via a positive R/C pulse. In this mode (read mode), the output data of the previous conversion is enabled during the high portion of R/C. A new transition begins with the falling edge of R/C, and the output of the three states returns to the hi-z state until the next high r/c.

conversion starts

Conversions on the ADS7800 are initiated only by the negative film that occurs on the R/C, as shown in Table I. No combination of other states or transitions will initiate the transition - Zion. Conversion is suppressed if CS or HBE is too high, or if it is too busy. CS and HBE should be stable at least 25ns before R/C transition. The timing relationship for starting the conversion is shown in Figure 8.

The busy output is low only during conversions and indicates the current state of the converter. During this time, the tri-state output buffer remains in the hi-z state, so data cannot be read during the conversion. During this period, additional conversions for the three digital inputs (cs, R/C, and HBE) are ignored, so conversions cannot be prematurely terminated or restarted.

Internal clock

The ADS7800 has an internal clock that is factory trimmed to achieve a typical conversion time of 2.47 microseconds and a maximum conversion time of 2.7 microseconds over the entire operating temperature range. No external adjustments are required, and a guaranteed maximum capture time of 300 microseconds guarantees throughput performance as transition pulses approach. 3 lbs.

read data

After a conversion is initiated, the output buffer remains in the hi-z state until the following three logic conditions are met; simultaneously: R/C high, busy high, CS low. After these conditions are met, the data lines are enabled according to the state of the hbe. See Figure 9 for timing relationships and specifications.

reference bypass

Pin 3 (REF) should be bypassed with a 22µF to 47µF tantalum capacitor. A rated operating voltage of 2V or higher is acceptable here. This pin is used to improve the system accuracy of the internal reference circuit and is not recommended for driving external signals. If there are important system reasons for using the ADS7800 reference externally, the output of pin 3 must be properly buffered.

"Hot Socket" Considerations

Two independent +5V vs pins 23 and 24 are used to minimize noise due to digital transients. If one pin is powered and the other is not, the ADS7800 may "latch up" and draw excessive current. In normal operation this is not a problem as the two pins will be soldered together. However, if there is a possibility of a "hot socket" during evaluation, incoming inspection, maintenance, etc., care should be taken to only power the ADS7800 after it has been socketed.

Minimize "glitches"

Coupling external transients into the A/D converter can lead to hard-to-debug errors. In addition to the previous discussion on power supply layout, bypassing, and grounding, there are other useful steps that can be taken to obtain the best analog performance of a system using the ADS7800. These potential sources of system problems are especially important when developing new systems and finding the cause of breadboard errors.

First, care should be taken to avoid glitches at critical times during the sampling and conversion process. Since the ADS7800 has an internal sample/hold function, it is critical that the signal that puts it into hold (R/C goes low) will be on any sample/hold amplifier. The R/C falling edge should be sharp with minimal rattle, especially within 20 ns after falling. Although usually not required, it is also a good practice to avoid failure of the ADS7800 when making bit decisions. Since the above discussion requires fast, clean rise and fall of r/c, it makes sense to keep the rising edge of the transition pulse outside the time when the bit decision is made. In other words, the switching pulse should be short (less than 100ns to switch before msb decision), or relatively long (greater than 2.75μs to switch after lsb decision).