The VSC8601KN package has been removed. The VSC8601XKN is still available.
Increased ESD voltage value. For charging device models it is ± 500 . The mannequin is ± 1500 .
Humidity sensitivity is now specified as level 3.
In the Jumbo packet register setting (28E.11:10), the packet length is updated.
The total power value at 2.5 V has been corrected in some current consumption specifications. The previous value increased slightly.
In the VDDIO DC characteristics at 3.3V, the input and output leakage current parameters (iileak and ioleak) increased from ±36µA to ±43µA.
In the VDDIO DC characteristic at 2.5 V, the minimum input high voltage (VIH) is increased from 1.7v to 2.0v. Input and output leakage current parameters (iileak and ioleak) increased from ±25µA to ±35µA.
Power-down mode and reset state.
In the AC characteristics of the CLKOUT pin, the duty cycle (duty cycle) is modified from a minimum of 40% to a minimum of 44% and a maximum of 60% to a maximum of 56%.
Also, the total jitter (jclk) has been increased from a maximum of 491ps to a maximum of 600ps, adding the qualifier "time interval error" to the condition.
In the SMI specification, the MDC rise and fall times are corrected from the minimum value to the maximum value.
Added a condition for the device reset rise time specification to measure from the 10% level to the 90% level.
In the rgmii uncompensated ac characteristic, the 1000base-t duty cycle (tduty1000) is split into two sets of values. In the first group, the value remains the same

Register 28E. 13:12 is set to 10 or 11. In the second group, the minimum value is 40% and the maximum value is 60%, condition: register 28E. 13:12 is set to 00 or 01.
In the AC characteristics of RGMII compensation, all setup and hold times have been modified from 0 ns maximum to 3 ns maximum.
In the description of pin MDIO, change the type from open channel (OD) to input and output (I/O).
The PLLMode pin description has been updated with additional clocking information. If A uses a crystal or an external 25MHz clock, pllmode must be pulled low. If one uses a 125MHz external clock, pllmode must be pulled high.
Added Design Guidelines for Serial Management Write Interface After Software Reset (SMI).
Added a design guideline about latency during connection.
Forced 100BASE-TX mode with automatic MDI/MDI-X detection enabled.
Removed the following design guidelines as they no longer apply to devices: remote fault state; DSP optimization script required; default port type incorrect; core 1.2V power supply needs to meet a specific range.
In the inline powered Ethernet switch diagram, the reference to "SGMII interface" has been corrected to "rgmii interface".
In the description of the CRC counter, the highest value of the CRC good counter is corrected from 10000 packets to 9999 packets, and then the counter is cleared.
The device version number is defined in the Identifier 2 register (address 3) and the JTAG device identifier.
In the DC characteristics of VDD33, VDDiomac or VDDiomicro at 3.3 V, the output leakage (ioleak) has been changed to the same value as the input leakage (ii leakage) with the same conditions (including internal resistors). Specifically, the values were changed from -10uA min and -10uA max to -36uA min and 36uA max.
At 2.5 V, the DC characteristics of the VDdiomac or VDdiomicro, the output leakage (ioleak) has been changed to match the value of the input leakage (iileak) to the same conditions (including internal resistors). Specifically, these values were changed from -10uA min and -10uA max to -25uA min and 25uA max.
At 2.5 V, the output high voltage parameter (VOH) erroneously indicates IOH = 1.0 mA in the DC characteristics of VDdiomac or VDdiomicro. It is now corrected for the condition Ioh=–1.0 mA.
When enabled for all current consumption specifications with on-chip switching regulators, the specification values for ivdd12 and ivdd12a are removed because

They were added unintentionally in a previous version of this document. The IVDD12 and IVDD12A values are used for current consumption with the regulator disabled.
For 100Base current consumption specifications, all reference speeds are revised from 100BASE-X to 100BASE-TX.
In the AC characteristics of the CLKOUT pin, the total jitter specification is supplementary. The typical value is 217 ps, the maximum value is 491 ps.
For device resets, the reset characteristics and timing diagrams are both updated to include new parameters: reset rise time (trst_rise) and power supply settling time (tvddstable). In the stress rating, the supply voltage parameter is removed because it is redundant.
In the pin description of TX_CLK, the rate of 10 Mbps is clarified as 2.5 MHz mode, 100 Mbps mode is 25 MHz, and 1000 Mbps mode is 125 MHz. Errata item "Rx_clk can reach up to 55% duty cycle" is still valid but all other errata items no longer apply to the latest part revision.
In the high-level block diagram, the representation of the XTAL pins goes from "xtal 1/2" to "xtal1" and "xtal2".
In the rgmii to cat5 block diagram, the interface name was changed from gmii to RGMII
Added new information on how to manually force a device to use MDI/MDI-X.
The VSC8601 device toggles between the low power state and the LP wake state every two seconds; as originally stated, the rate is not programmable.
While the link partner is awake, the device sends two-second FLP pulses; as originally stated, they are not limited to three bursts.
In the PHY address description for the Serial Management Interface (SMI), the physical address has been corrected from 3:0 to 4:0.
For the enhanced LED method, controlled by MII register 16E, where two LED modes are changed. Mode 11, Send activity and Mode 13, Receive activity are now reserved.
In the description of the remote loopback test feature, the control register bit was revised from 23.3 to 27E.10.
For the JTAG interface commands extest and sample/preload, the value of the register width is changed from tbd to 45.
For the mode control register (address 0), rgmii in-band signaling will have no effect when bit 11 (power down) is set.

In the Identifier 2 register (address 3) to enable device identification, the default value of bits 9:4 was modified from tbd to 000010.
In the LED control register (address 27), the names of bits 2 and 1 were corrected from "link/active" to simply "active".
In active control (address 20E), bit 5 was reassigned from reserved to the mac rx_clk disable parameter.
In the Extended PHY Control 4 register (Address 23E), all bits are set to false. It has now been restored.
In the Extended PHY Control 5 register (Address 27E), the settings have been changed for bits 8:6 and 5:3 (100BASE-TX and 1000BASE-T transmitter amplitude control).
For bits 8:6 (100BASE-TX), setting 011 changed from +5 amplitude to reserved, making bit setting 010 (+4 amplitude) maximum. For bits 5:3 (1000BASE-T), setting 011 changed from +3 amplitude to reserved, making bit setting 010 (+2 amplitude) maximum.
For greater clarity, a table listing device functions and associated CMode pins now references the associated registers and bits for each function.
Added some address locations and made corrections to the introduction to the EEPROM configuration table of contents.
Additional conditions have been added to the DC electrical specifications for VDDIO at 3.3 V and 2.5 V. This specification is only considered valid when vddreg=3.3 volts.
with a new set of specifications.
The minimum and maximum values are modified for vddiomicro, vddiomac and vdd33 parameters at 3.3v under recommended operating conditions.
For all these parameters, the minimum value changed from 3.13 V to 3.0 V, and the maximum value changed from 3.47 V to 3.6 V. The VDDREG parameter has been added to the recommended operating conditions.
In the stress rating, a new rating for the VDDREG parameter has been added.
Added Errata section.

product description
The VSC8601 device is a low-power Gigabit Ethernet (GBE) transceiver ideal for local area network applications on Gigabit motherboards. The device is a compact, plastic low-profile quad flat-panel package with exposed pad (LQFP) that is the best choice for applications that are sensitive to package outlines.
Vitesse's mixed-signal and digital signal processing (DSP) architecture ensures robust performance. It supports half-duplex and full-duplex 10BASE-T, 100BASE-TX and 1000BASE-T communication speeds over Category 5 (Category 5) Unshielded Twisted Pair (UTP) cables with distances greater than 140 m, showing that the next cable Good tolerances for FEXT, ECHO and other types of environmental and system electrical noise.
The figure below shows a high-level generic view of the VSC8601 application.
Figure 1. Typical Application

Features This section lists key aspects of the VSC8601 device functionality and design that differentiate it from similar products:
10/100/1000BASE-T physical layer, the lowest power consumption in the industry.
Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T) specifications.
Supports RGMII version 1.3 and 2.0 (2.5 V, 3.3 V) Mac interface.
Low EMI line driver with integrated line side termination resistors.
Supports jumbo frames up to 16 KB at all speeds.

Three programmable direct drive LEDs.
Test mode suite including loopback path, Ethernet packet generator and CRC
counter.
Veriphy® kits provide extensive network cable information such as cable length, termination status, and open/short fault locations.
actiphytm power saving mode.
Advanced power management complies with Wake on LanTM and PCI2.2 power requirements.

Traditional Power over Ethernet (PoE) is supported.
Powered by a single 3.3 V supply using an optional on-chip switching regulator. Supports IEEE1149.1 JTAG boundary scan. 10 mm x 10 mm, 64-pin, plastic LQFP package with exposed pad.
application
Suggested applications for the VSC8601 device include: LANISCSI and TOE applications on motherboards, network cards and mobile PCs Workgroups, Desktop switches and routers Gigabit Ethernet SAN, NAS and Metro network systems Network enabled devices such as printers, IP phones and Gaming Devices ATcatm 3.0 and PicmgTM 2.16 Ethernet Backplane Applications

Block Diagram The following diagram shows the main functional blocks of the VSC8601 device.
High-level block diagram

Functional Description This section provides detailed information on how the VSC8601 device works, as well as providing configuration and operational features, and how to test its functionality. It includes descriptions of various device interfaces and how to set them up.
Interfaces and Media
The VSC8601 device operates using the interfaces and media shown in the table below with illustrations.
rgmii to cat5 block diagram

MAC interface
vsc8601 supports rgmii version 1.3 and 2.0 (2.5v, 3.3v) mac interface.
MAC Resistor Calibration To simplify board design, the vsc8601 mac interface uses a simplipintm output that can self-calibrate to the desired impedance characteristics to eliminate the need for series termination resistors. By default, these RX output pins are calibrated to 50Ω. Additionally, MII register 19E, bits 15:14 can be used to select a different target impedance. For rgmii mac interface mode the rgmii interface can support all three speeds (10 Mbps, 100 Mbps and 1000 Mbps) and serve as the interface for rgmii compatible macs.

rgmii mac interface

5 types of media interface
The twisted pair interface on the VSC8601 conforms to the IEEE802.3-20005 class media specification. The VSC8601 is different from other gigabit physics in that it is a passive component (requires the cat5 interface of the phy to be connected to an external 1:1 transformer) fully integrated into the device. The connection interface of twisted pair is shown in the figure below.

Type 5 media interface Type 5 auto-negotiation

The VSC8601 device supports the twisted pair auto-negotiation IEEE standard 802.3-2000 defined in Clause 28. The auto-negotiation process includes evaluating the phy and its link partners to determine the optimal mode of operation, throughput speed, duplex configuration, and master-slave mode of operation
1000 BASE-T settings. Autonegotiation also allows connected MACs to communicate through the vsc8601 device using an optional "next page" link partner MAC, which sets properties that cannot be defined by the IEEE standard.
In installations where the cat5 link partner does not support auto-negotiation, the VSC8601 automatically switches to using parallel detection to select the appropriate link speed.
Clear VSC8601 device register 0, bit 12 to disable clause 28 twisted pair auto-negotiation. If auto-negotiation is disabled, the state of the register bits is 0.6, 0.13,

and 0.8 determine the operating speed and duplex mode of the device manual MDI/MDI-X settings as an alternative to automatic MDI/MDI-X detection (using HP Auto MDIX technology),
Automatic Crossover and Polarity Detection For trouble-free configuration and management of Ethernet links, the VSC8601 appliance includes robust, automatic, media-dependent, and crossover-media-dependent detection capabilities, HP Auto MDIX, three available speeds (10Base -T, 100BASE-T and 1000BASE-T) In addition, the device detects and corrects polarity errors on all MDI pairs, a useful capability beyond what is required by the standard.
Both HP automatic MDIX detection and polarity correction are enabled by default in the device. The default setting can be adjusted using device register bits 18.5:4. The status bits for these functions are located in register 28.
VSC8601 product introduction function description
The HP Auto MDIX algorithm of the VSC8601 device successfully detects, corrects, and operates on combinations using any of the MDI wiring pairs listed in the table below. NOTE: The VSC8601 device can be configured to perform HP auto-MDIX even if it disables auto-negotiation (set register 0.12 to 0) and forces the link to run at 10/100 speed. To enable this feature, set Register 27E.15 to 0.
Link Speed Downshift For operation in cabling environments that are not 1000BASE-T compatible, the VSC8601 device provides an automatic link speed "downshift" option. When enabled, the device automatically changes its 1000BASE-T auto-negotiation advertisement to the next slower speed after the next number of failed 1000BASE-T attempts. This is useful for networks installed with older cables (which may only include pair A instead of pairs C and D).
Transformerless Ethernet
The cat5 media interface supports 10/100/1000bt Ethernet for backplane applications such as the eight-pin channel specified in the picmgtm 2.16 and atcatm 3.0 specifications. With proper AC coupling, a typical class 5 transformer can be removed and replaced with a capacitor.
Ethernet Inline Powered Devices
The vsc8601 device can detect inline powered device applications in Ethernet. Its inline power detection capability can be used to allow IP phones and other devices (such as wireless access points) to receive power directly from an Ethernet cable, similar to switching over a telephone cable from a private branch exchange (PBX) office. This can does not require the IP phone to have an external power supply. It can also maintain an active inline powered device during a power outage (assuming the Ethernet switch is connected to an uninterruptible power supply, battery, backup power generator, or other uninterruptible power supply).
abdcnormalmdiB ACD standard MDI-X for pair swapping on pairs c and d, pair swapping on pairs C and D VSC8601 Product Introduction Functional Description
The VSC8601 device is paired with a system used to power data terminal equipment (DTE) using MDI or Twisted, as described in IEEE Standard 802.3af Clause 33. The image below shows an example of such an application.

Inline Powered Ethernet Switch Diagram

The following procedure describes what an Ethernet switch must perform to process an inline power request from a link partner (LP) to receive inline power.
1. Use its serial management interface. Set register bit 23e.10 to 1.
2. Make sure the VSC8601 device auto-negotiation enable bit (register 0.12) is also set to 1. In application, the device sends a special Fast Link Pulse (flp) signal to the LP. Read register bit 23E. 9:8 The search requires Power over Ethernet (PoE).
The vsc8601 phy monitors the input of the flp signal of the lp loopback. An when flp is off. This condition is reported when the VSC8601 device register bits 23E.9:8 Readback 01. It can also be deasserted by a subsequent clear, after-read interrupt. If the LP device does not loop the FLP after a certain time, the VSC8601 device register bits 23E.9:8 are automatically reset to 10.
4. If the VSC8601 PHY reports that the LP requires PoE, the Ethernet switch must enable inline power on this port, external to the PHY.
5. If VSC8601
Device register bits 23E.9:8 are automatically reset to 10 and then automatically change their normal auto-negotiation process. It is then established when the link is auto-negotiated and the link status bit is set (register bit 1.2 is set to 1).
6. In case of link failure (indicating 0 when VSC8601 device register bit 1.2 is read), it should be disabled at the physical layer. The vsc8601 phy disables its normal auto-negotiation process and re-enables its inline powered device detection mode.
Active Power Management In addition to the IEEE-specified power-down control bits (device register bit 0.11), the device includes an Actiphy™ power management mode for each phy. This mode supports power-sensitive applications such as Wake-on-LAN™ functionality. It utilizes a signal detection feature to monitor the media used to determine when to automatically shut down the physical layer. PHYs "wake up" at programmable intervals and attempt to "wake up" to link partner PHYs by sending flp bursts over the copper medium.
The active power management mode in the VSC8601 device can be enabled for normal operation at any time by setting register bit 23.5 to 1.
When active mode is enabled, three operating states are possible: Low power state
LP wake-up state normal working state (connected state)
The VSC8601 device detects signal energy on the media interface pins after every two seconds. When the signal detects energy, the physical layer enters the normal working state. If the physical layer is in its normal working state and the link fails, the phy in link state timeout timer has expired. After reset, the phy enters a low power state.
When auto-negotiation is enabled in phy, the operation of the actiphy state machine is described below. If auto-negotiation is disabled and the link is forced to 10bt or 100btx while the phy is in the low power state, the phy continues in the low power and LP wake state until signal energy is detected on the media pin. At this point, the phy transitions to a normal operating state and remains in that state even if the link is disconnected. If the phy is in a normal operating state, when the link goes down, the phy remains in that state without transitioning back to a low power state. Subsequent clear, interrupt deasserted after read. If the LP device does not loop the FLP after a certain time, the VSC8601 device register bits 23E.9:8 are automatically reset to 10.
4. If the VSC8601 PHY reports that the LP requires PoE, the Ethernet switch must enable inline power on this port, external to the PHY.
5. If VSC8601
Device register bits 23E.9:8 are automatically reset to 10 and then automatically change their normal auto-negotiation process. It is then established when the link is auto-negotiated and the link status bit is set (register bit 1.2 is set to 1).
6. In case of link failure (indicating 0 when VSC8601 device register bit 1.2 is read), it should be disabled at the physical layer. The vsc8601 phy disables its normal auto-negotiation process and re-enables its inline powered device detection mode.
Active Power Management In addition to the IEEE-specified power-down control bits (device register bit 0.11), the device includes an Actiphy™ power management mode for each phy. This mode supports power-sensitive applications such as Wake-on-LAN™ functionality. It utilizes a signal detection feature to monitor the media used to determine when to automatically shut down the physical layer. PHYs "wake up" at programmable intervals and attempt to "wake up" to link partner PHYs by sending flp bursts over the copper medium.
The active power management mode in the VSC8601 device can be enabled for normal operation at any time by setting register bit 23.5 to 1.
When active mode is enabled, three operating states are possible: Low power state
LP wake-up state Normal working state (connected state) The VSC8601 device detects signal energy on the media interface pins after every two seconds. When the signal energy is

The following diagram shows the relationship between activity states and timers.

Active status
10.1 Low Power State In the low power state, all major digital blocks are powered down. However,
Provides the following functions:
SMI interface (MDC, MDIO, MDInt)
In this state, the phy monitors the signal energy of the media interface pins. The physical layer transitions from a low power state to a normal operating state when signaled to detect energy on the medium. When phy is connected to the following:
Auto-negotiation capable link partners cannot auto-negotiate (blink/force) link partners (100BASE-TX or 10BASE-T)
Another PHY in the active LP wakeup state in the absence of signal energy on the media pin, the PHY from the programmable sleep-based low voltage periodic wakeup timer (register bits 20E.14:13). The actual sleep time is random –80 ms to +60 ms to avoid two link Phys in active mode from going into a locked state Link partner wake-up state during operation In this state the phy tries to wake up the link partner. flp pulses were sent to alternate pairs A and B of Cat5 medium for two seconds. In this state, the following functions are provided: SMI interface (MDC, MDIO, MDInt)
The phy returns to a low-power state after Kercourt has sent the signal energy on the associated medium.
Normal working state In this state, the phy establishes a link with its link partner. When the medium is disconnected or the link partner is powered down, the phy will wait for a programmable link state timeout timer, using register bits 28.7 and 28.2. Then enter a low power state.
Serial management interface
The vsc8601 device includes an IEEE 802.3 compliant Serial Management Interface (SMI) affected by the use of its MDC and MDIO pins. SMI provides control and status registers for the device. The register set that controls smi consists of 32 16-bit registers, including all necessary ieee-specific registers.
SMI is a synchronous serial interface with bidirectional data on the MDIO pin, that is, clocked on the rising edge of the MDC pin. The clock frequency of the interface can be from 0 MHz to 25 MHz, depending on the total load on the MDIO. External, 2 kΩ pull-up resistor is required on the MDIO pin.
SMI Frame Data is transmitted over SMI, using 32-bit frames, with optional and arbitrary preamble lengths. The following figure shows the SMI frame format operation for read and write operation.

The terms used in Figure 8 and the idle period during which the MDIO node will enter a high impedance state are provided below. This allows an external pull-up resistor to pull the MDIO node to a logic 1 state. Because lazy mode should not contain any conversions on MDIO, the number of bits is undefined when idle.
The preamble is not expected nor required by default. The preamble is a string. If present, the preamble must be at least one bit; otherwise, it may be of arbitrary length.
Start of Frame (SFD) mode 01 indicates the start of a frame. If the pattern is not 01, all the following bits will be ignored until the next preamble pattern is detected. Read or write opcode mode 10 indicates read. Mode 01 means write. If these bits are not 01 or 10, the preamble pattern is detected next.
The phy address vsc8601 only matches its physical address when the physical address is received. Physical addresses are 5 bits long (4:0).
bit is set by the cmode pin. The last five bits of the register address are the register address.
When a read operation is performed on MDIO it is called a Turn Around (TA) bit. During a read operation, the VSC8601 device drives the second TA bit, logic 0.
16-bit data read from or written to a device is considered a data or data stream. When reading data from phy, it is on the next rising edge of MDC to MDC. When data is written to phy, it must be valid around the rising edge of MDC.
Idle the sequence repeats.
SMI interrupt
The smi also includes an output interrupt signal, mdint, which is used to signal the station manager when certain events occur in the phy.
The MDINT pin can be accessed by connecting the pin to a pull-up resistor and to VDDdio. The figure below shows this configuration.

MDint configured as an open-drain (active low) pin

mdint configured as an open source (active high) pin When the phy generates an interrupt, the mdint pin is asserted (driven high or low, depending on the resistor connection) if the interrupt pin enable bit (MII register 25.15) is set.

LED interface
The VSC8601 device can directly drive up to three LEDs. All LED outputs are active low and driven by VDD33 supply 3.3V. When activated, the pin is primarily used to sink current from the cathode side of the LED, but the pin can also provide power to the anode portion of the LED when it is not activated. This allows the use of two LED pins to drive multi-state bi-color LEDs.
Simple or Enhanced LED Method
The VSC8601 provides two methods of controlling LEDs: simple or enhanced. This simple LED method is backward compatible with the LED control found in previous Vitesse Ethernet PHY devices. The simple LED approach simplifies software backward compatibility for customers switching to the VSC8601. The Easy LED method is controlled by MII register 27, enabled by default.
For added flexibility, the enhanced LED control VSC8601 LED method can be used. Enable the enhanced LED method by setting MII register 17E.4 = 1. when? When enabled, the LEDs are controlled by MII registers 16E and 17E. The setting of MII register 27 is ignored.
Simple LED method When MII register 17E.4 = 0, the LED is by the simple LED method. This LED method is enabled at power-up and is registered by the MII control 27. In this method, the mii register 27 controls the LEDs.
Enhanced LED Method When MII register 17E.4 = 1, the LEDs are enhanced by the Enhanced LED method. In this method, mii registers 16e and 17e control the leds
LED Modes If you are using the enhanced LED method, there are several LED modes available.
They are located in MII register 16E. Each LED pin can be configured to display different status information. Set the led mode pin settings using register 16e or in conjunction with cmode. The following table summarizes the LED functions.
Note that the modes listed in the table below configure each LED pin with Register 16E. For the listed LED states, 1 = pin is held high (de-asserted), 0 = pin is held low (asserted), blinking/pulse stretching depends on the LED behavior setting in Register 17E.

LED Behaviors Some LED behaviors can be programmed into the VSC8601 device. Use the program in setup register 17e to bootstrap behavior, including the following: LED combine enables LEDs to display primary and secondary modes. This can be enabled or disabled for each LED pin. For example, a copper link running in 1000BASE-T mode and current activity can display a LED pin configured for Link1000/Activity mode. When linking, the LED asserts for the 1000Base-T partner when activity is sent by the phy or received by the link partner. Combine function disable only allows the state of the selected main function. In this example, only the Link1000 asserts the LED if the combine function is disabled.
LED blinking or pulse stretching This behavior is used for activity and crash indication.
This allows unique configuration for each LED pin. Activity and collision events may occur randomly and intermittently throughout the connection. Active or Collision visually provides both modes. Blinking is a 50% duty cycle oscillating deassertion and de-assertion LED pin. Pulse stretching guarantees that the LED is de-asserted for a specific period of time if activity is present or not. These rates can also be configured using register settings.
LED Blink or Pulse Stretch Rate Controls the LED blink rate or pulse stretch length when blink/pulse stretch is enabled on the LED pin. The blink rate alternates between high and low voltage at 50% duty cycle and can be set to Hz, 5 Hz, 10 Hz or 20 Hz. For pulse stretching, it can be set to 50 ms, 100 ms, 200 ms or 400 ms.
LED Pulse Enable provides additional power savings, and the LED (when asserted) can be pulsed at 5 kHz, 20% duty cycle.
Test features
The vsc8601 device includes several test functions designed to enable performing system-level debugging and in-system production testing. This section describes the available functions.
The Ethernet Packet Generator (EPG) device EPG can be used in each of the 10/100/1000BASE-T speed settings to isolate between the MAC and the vsc8601 device or the locally connected phy and its remote link partner. Effectively enabling the EPG function will disable all MAC interface transmit pins and select EPG as the source for all data transfer to the twisted pair interface.
Note: EPG is for use in laboratory or system test equipment only. Do not use the EPG test function network when the VSC8601 device is connected to an active device.
To enable the VSC8601 device EPG function, set the device register bit 29E.15 to 1.

EPG is enabled. If you also need to disable the mac receive pins, set register bits 0.10 to 1. When the device register bit 29e.14 is set to 1, the phy starts transmitting Ethernet packets based on the settings in registers 29e and 30e. These register settings: Source address and destination address of each packet Packet size Packet Interval Future Combat System Status Transmission Duration Payload Mode If register bit 29E.13 is set to 0, then register bit 29E.14 is transmitted at 30000000 data pack.
CRC counter at
VSC8601 device. There is a 14-bit crc good counter in register bit 18e as well as a separate 8-bit CRC error counter, available in register bits 23E.7:0. The device CRC counter works in 10/100/1000BASE-T tests as follows: After a packet is received on the media interface, register bit 18e.15 is set and cleared after reading. Then, the packet is counted by the crc good count counter or the CRC error counter. Both CRC counters are also automatically cleared when reading.
The highest value of the CRC good counter is 9999 packets. When the next packet is received, the counter will clear and continue counting other packets beyond this value. When the CRC error counter reaches its maximum counter limit, it saturates for a total of 255 packets.
Far End Loopback The far end loopback test function can be enabled by setting register bit 27E.10 to 1. When enabled, it forces incoming data from the link partner on the current media to be retransmitted back to the link partner's interface on the media interface, as shown in the figure below. In addition, incoming data will also appear on the data pins of the mac interface on the receiving end. Data present on the mac's transmit data pins will ignore the interface when using this test function.