application

Photodiode Preamplifier

battery powered meter

Power Control and Protection

Medical instrument remote sensor

Low Voltage Strain Gauge Amplifier

dac output amplifier

General Instructions

The AD824 is a quad, FET input, single-supply amplifier with rail-to-rail outputs. The combination of FET input and rail-to-rail output makes the AD824 useful in a variety of low-voltage applications where low input current is a major consideration. The AD824 is guaranteed to operate from a single 3V supply to a dual ± 15V supply. The parametric performance of the AD824AR-3V at 3V is fully guaranteed.

Manufactured on Analog Devices' complementary bipolar process, the AD824 has a unique input stage that allows the input voltage to safely exceed the negative and positive supplies without any phase reversal or latch-up. The output voltage fluctuates within 15 mV of the power supply.

Capacitive loads up to 350 pf can be handled without oscillation.

The FET input combined with laser trimming provides an input with very low bias current, guaranteed to be less than 1 mV. This enables high precision designs even at high source impedances. The combination of accuracy and low noise makes the AD824 ideal for use in battery-operated medical equipment.

Applications for the AD824 include portable medical equipment, photodiode preamplifiers, and high impedance sensor amplifiers.

The output is capable of swinging rail-to-rail, which enables designers to build multistage filters in a single-supply system while maintaining a high signal-to-noise ratio.

Specified over the extended industrial (–40°C to +85°C) temperature range, the AD824 is available in a narrow 14-lead SOIC package.

theory of operation

Input characteristics

In the AD824, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. The minimum input common mode voltage extends from 0.2v below -vs to 1v below +vs. Driving the input voltage close to the positive rail results in a loss of amplifier bandwidth.

The AD824 does not exhibit phase reversal when the input voltage is less than or equal to +V. Figure 30A shows the AD824 voltage follower response to a 0 V to 5 V (+vs) square wave input. Input and output are overlapping. The output tracks the input up to +vs without phase reversal. Bandwidth reduction above the 4V input results in rounding of the output waveform. For input voltages greater than +V, a resistor in series with the non-vertical input prevents phase inversion at the expense of greater input voltage noise. As shown in Figure 30b.

Because the input stage uses an n-channel jfet, the input current during normal operation is positive; the current flows from the input. If the input voltage drives a positive voltage greater than +V 8722 ; 0.4 V, the input current reverses as the internal device junctions become forward biased.

Combining the current limiting resistor with the AD824 will apply the input voltage to the AD824 if the input voltage exceeds the possibility of exceeding the positive supply by more than 300 mV, or when ±V = 0 V. The amplifier will be damaged if left in this condition for more than 10 seconds. A 1kΩ resistor allows the amplifier to withstand continuous overvoltages of up to 10v and increases the input voltage noise to a negligible level.

Input voltages below -V are a completely different situation. As long as the total voltage from +vs to the input terminals is less than 36v, the amplifier can safely withstand input voltages below -vs 20v. In addition, the input stage typically maintains a pico-amp input current within this input voltage range.

Output characteristics

The unique bipolar rail-to-rail output stage of the AD824 swings within 15 mV of positive and negative supply voltages. The approximate output saturation resistance of the AD824 is 100Ω. This can be used to estimate the output saturation voltage when driving larger current loads. For example, at a current load of 5 mA, the saturation voltage of either supply is 0.5 volts.

When the load resistance exceeds 20kΩ, the input error voltage of the AD824 is almost constant until the output voltage is driven to 180mV of either supply.

If the output of the AD824 is overdriven to saturate either output device, the amplifier will return to the amplifier's linear operating region within 2µs of its input. Direct capacitive loads will interact with the amplifier's effective output impedance, creating an additional pole in the amplifier's feedback loop, which can cause excessive peaking or loss of stability in the impulse response. The worst case is that the amplifier is used as a unity gain follower. The impulse response of the AD824 as a unity-gain follower driving 220 pF. The smaller the loop gain and the smaller the loop bandwidth configuration, the less sensitive it is to the effects of capacitive loading. The noise gain is the inverse of the feedback attenuation factor provided by the feedback network used. Figure 31 shows a method for extending the drive capability of a unity-gain follower capacitive load. Using these component values, the circuit drives 5000 pf with 10% overshoot.

application information

Single Supply Voltage-Frequency

converter

The circuit shown in Figure 32 uses the AD824 to drive a low-power timer that produces a stable pulse of width T1. The positive output pulse is integrated by r1 and c1 and used as one input of the ad824, which is connected as a differential integrator. The other input (unloaded) is the unknown voltage V. The AD824 output drives the timer trigger input, closing the entire feedback loop. At a typical 2 Pa AD824 bias current allows source impedance in the MΩ range with negligible dc errors. This circuit achieves a linearity error of 0.01% of full scale. This performance is obtained with a single 5v supply that provides less than 3ma of current to the entire circuit.

notes

fout=vin/(vref×t1), t1=1.1×r3×c6=25khz fs, as shown in the figure.

*=1% metal film, <50ppm/℃tc**=10%, 20t film, <100ppm/℃tc; T1=33 microseconds, FOUT=20kHz@VIN=2.0V.

Single-Supply Programmable Gain Instrumentation Amplifier

The AD824 can be configured as a single-supply instrumentation amplifier capable of operating from single-supply to 5 volts or dual-supply to ±15 volts. A bias current of 2 Pa at the AD824 FET input minimizes offset errors caused by high unbalanced source impedances. A precision thin film resistor array sets the input amplifier gain to 10 or 100. These resistors are laser trimmed to match 0.01% ratios with a maximum temperature difference of 5ppm/°C.

3V, Single Supply Stereo Headphone Driver

The AD824 shows good current drive and THD+N performance even on a single 3V supply. At 1 kHz, the total harmonic distortion plus noise (THD+N) of a 300 mV PP output signal equals -62 dB (0.079%). This is comparable to other single-supply op amps, which consume more power and cannot operate on a 3V supply.

In Figure 35, the input signal to each channel is capacitively coupled through 1 μf Mylar. The resistive divider sets the DC voltage at the non-vertical input so that the output voltage is between the supplies (1.5 V). The gain is 1.5. Each half of the AD824 can be used to drive the headphone channel. A 5hz high pass filter is implemented with a 500µf capacitor and a headphone, which can be simulated as a 32Ω load resistor to ground. This ensures that all signals in the audio range (20 Hz to 20 kHz) are delivered to the headphones.

Low Dropout Bipolar Bridge Driver

The AD824 can be used to drive a 350Ω Wheatstone bridge. Figure 36 shows half of the AD824 used to buffer the AD589-A 1.235V low power reference. The 4.5v output can be used to drive the adc front end. The other half of the AD824 is configured as a unity gain inverter and generates another 4.5 V bridge input. Resistors R1 and R2 provide constant current for the bridge excitation. The AD620 low power instrumentation amplifier is used to regulate the differential output voltage of the bridge. The gain of the AD620 is programmed using an external resistor, R, and is determined by: G

A 3.3 V/5 V precision sample and hold

amplifier

In battery powered applications, low supply voltage op amps require low power consumption. Additionally, low supply voltage applications limit the signal range of accurate analog circuits. Circuits such as the sample-and-hold circuit shown in Figure 37 illustrate techniques for designing precision analog circuits in low supply voltage applications. To maintain a high signal-to-noise ratio (snr) in low supply voltage applications, rail-to-rail, input/output op amps are required. This design highlights the AD824's ability to operate rail-to-rail from a 3V/5V supply, with the advantage of high input impedance. The AD824 is a quad JFET input op amp that is ideal for sample and hold circuits due to its low input bias current (3 Pa, typ) and high input impedance (3 × 10 Ω, typ). The supply current of the AD824 is also low, so the total supply current for this circuit is less than 2.5 mA.

In many single-supply applications, a false-grounded generator is required. In this circuit, r1 and r2 distribute the supply voltage symmetrically, creating a false ground voltage at half the supply. Amplifier a1 then buffers this voltage to produce a low impedance output drive. The sample-and-hold circuit is configured in an inverted topology around this false ground plane.

A design consideration for a sample-and-hold circuit is the output voltage drop due to op amp bias and switch leakage current. By choosing a jfet op amp and a low-leakage cmos switch, this design reduces the sag rate error to more than 0.1µv/µs. A higher ch value will result in a lower sag rate. For best performance, CH and C2 should be polystyrene, polypropylene or teflon capacitors. These types of capacitors have low leakage and low dielectric absorption. Additionally, 1% metal thin film resistors are used throughout the design.

In sampling mode, SW1 and SW4 are closed and the output is V=-vin. The purpose of sw4, working in parallel with sw1, is to reduce pedestal or hold step error by injecting the same amount of charge into the non-rotating input of a3 as sw1 injects into the inverting input of a3. This creates a common-mode voltage at the input of A3, which is then rejected by A3's CMR; otherwise, the charge injection of SW1 creates a differential voltage step error that occurs at V. The pedestal error of this circuit is less than 2 mV over the entire 0 V to 3.3 V/5 V signal range. Another way to reduce pedestal error is to reduce the amplitude of the pulses applied to the control pins. To control the ADG513, only 2.4 V is required for the on state and 0.8 V for the off state. If possible, use an input control signal with an amplitude range of 0.8 V to 2.4 V instead of an input control signal with a full range of 0 V to 3.3 V/5 V for minimal pedestal error. Other circuit features include less than 3 microseconds to 1% acquisition time; reducing ch and c2 will further speed up acquisition time, but will result in increased pedestal error. The stabilization time is less than 300ns to 1%, and the sampling mode signal bw is 80khz.

The ADG513 was chosen for its ability to operate with 3V/5V supplies and has precision CMOS switches that are normally open and normally closed during dielectric isolation. SW2 is not needed in this circuit; however, it is used in parallel with SW3 to provide a lower R analog switch.