describe
The vfc110 voltage-to-frequency converter is the third generation of vfc with better features and performance. These include higher frequency operation, an onboard precision 5V reference, and a disable function.
A precision 5V reference can be used to compensate for VFC transfer functions and to excite sensors or bridges. Enable pins allow the outputs of multiple VFCs to be paralleled, multiplexed, or simply turn off the VFCs. The open collector frequency output is TTL-/CMOS compatible. Outputs can be isolated using optocouplers or transformers.
Internal input resistors, one-shot and integrator capacitors simplify application circuits. At 10V input, these parts are tuned for a full-scale output frequency of 4MHz. Many applications do not require additional components.
The VFC110 is packaged in a 14-pin plastic dip. Industrial and military temperature range ratings are available.

operate
Connections required for operation at 4MHz full-scale output frequency. This mode of operation only requires power supply bypass capacitors and output pull-up resistor RPU. An input voltage of 0V to 10V produces an output frequency of 0Hz to 4MHz. The internal input resistor, primary, and integrator capacitors set the full-scale output frequency. This input is applied to the summing junction of the integrator amplifier through a 25kΩ internal input resistor. Pin 14 (non-vertical amplifier input) should point directly to the negative side of the VIN. The common-mode range of the integrating amplifier is limited to approximately -1V to +1V (referenced to analog ground). This enables the Kelvin's non-vertical input to sense the VIN's common connection, easily adapting to any ground faults. The input impedance loading vin is equal to the input resistance of about 25kΩ.

Low Frequency Operation The VFC110 can operate at lower frequencies by limiting the input voltage to less than the nominal 10V full-scale input. However, to maintain the 10V fs input and maximum accuracy, external components are required (see Table 1). Minor adjustments to the nominal values shown may be required. The integrator and one-shot capacitor are connected in parallel with the internal capacitor. Figure 2 illustrates the connections required for a 100kHz full-scale output. The one-shot capacitor cos should be connected to logic ground. The primary connection (pin 6) is not short-circuit protected. A short circuit to ground can damage the device.
The value of the integrator capacitor does not directly affect the output frequency, but rather determines the magnitude of the integrator output voltage fluctuation. Using cint equal to cos provides an integrator output swing from 0v to about 1.5v.
Component Selection The choice of external resistor and capacitor type is important. Temperature drift of external input resistors and one-shot capacitors can affect the temperature stability of the output frequency. NPO ceramic capacitors usually give the best results. The silver mica type will result in slightly higher drift, but may be adequate in many applications. rin should use low temperature coefficient thin film resistors.
The integrator capacitor acts as a charge bucket where charge is accumulated from the input, VIN (vin), and this charge is depleted during one discharge. While the size of the barrel (capacitance value) is not critical, it cannot leak. Capacitor leakage or dielectric absorption can affect the linearity and offset of the transfer function. High quality ceramic capacitors are available for values less than 0.01µf. Be careful with high value ceramic capacitors.

4MHz full-scale operation high-k ceramic capacitors may have voltage nonlinearity that degrades overall linearity. Polystyrene, polycarbonate, or polyester film capacitors are superior high value.

pull-up resistor
The VFC110 frequency output is an open collector transistor. The pull-up resistor should be connected from FOUT to the logic supply voltage, +VL. The output transistor turns on during one trigger, causing the output to be logic low. The current in this resistor should be limited to 8mA to ensure a maximum logic low of 0.4V. The value chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on FOUT results in a slow, rounded rising edge at the end of the output pulse. This effect can be minimized by using a pull-up resistor, which sets the output current to a maximum of 8ma. The logic supply can be any positive voltage up to +vs.

If the enable pin is not connected, the enable input will assume a logic high level, enabling operation. Alternatively, the enable input can be connected directly to +vs. The enable input can be driven by an open collector logic signal due to the inclusion of an internal pull-up current.
A logic low on the enable input causes the output pulses to stop. This is accomplished by interrupting the signal path through the one-shot circuit. When disabled, all circuits remain active and quiescent current does not change. Since no reset current pulse occurs when disabled, any positive input voltage will cause the integrator op amp to ramp negatively and saturate at its maximum negative output swing of about -0.7V.

Oscillation is regulated by the current balance (or charge) between the input current and
The VFC110 uses a charge balancing technique to obtain a time-averaged reset current. The current equations achieve high precision. At the heart of this technique is balance: an analog integrator consisting of an integrator op amp, feedback capacitor CINT, and input resistor RIN. The output voltage of the integrator is the same as I charge stored in CINT at the I IRF duty cycle. The input voltage is generated at the input being forced into the vin/rin current ref oR through CINT. This current charges cint, resulting in where to is a discharge cycle and fout is the negative rise of the integrator output voltage. Oscillation frequency.
When the output of the integrator goes to 0V, the comparator trips, triggering a trigger. This connects the reference current iref (about 1 mA) to the integrator input tos during one trigger. This switch current ramps the integrator output in a positive direction until the end of a trigger cycle. Then the cycle starts again.

The VREF output can be used to compensate the transfer function and excite the sensor. Figure 3 shows the vref used to shift the transfer function of vfc110 to achieve a bipolar input voltage range. Subsurface Zener reference circuits are used for low noise and good temperature drift. The output current is specified at 10mA and the current is limited to about 20mA. Excessive or variable loads on VREF can degrade frequency stability due to internal heating.
Measuring the output frequency To complete the integral A/D conversion, the output frequency of the VFC110 must be calculated. Simple frequency counting is done by counting the output pulses at a reference time (usually derived from a crystal oscillator). This can be accomplished with counter/timer peripheral chips from many popular microprocessor families. Many microcontrollers have counter inputs that can be programmed for frequency measurement.
Since fout is an open collection device, negative-going edges provide the fastest logic transitions. In noisy environments, clocking the counter on the falling edge will provide the best results.
Frequency can also be measured by precisely timing one or more cycles of the VFC output. The frequency must then be calculated as it is inversely proportional to the measurement period. This measurement technique provides high measurement resolution with short conversion times. This is the approach taken by most high performance laboratory frequency counters. An offset transfer function is usually required, so a 0V input results in a finite frequency output. Otherwise, the output period (and therefore the transition time) approaches infinity.
Frequency Noise Frequency noise (small random changes in output frequency) limits the effective resolution of fast frequency measurement techniques. The effects of frequency noise are averaged over a long period of time for maximum useful resolution. The VFC110 is designed to minimize frequency noise and allow for useful resolution improvements in short measurement times. A typical characteristic curve frequency count repeatability versus count gate time shows that noise has an effect as the count gate time varies. It shows one standard deviation (1σ) count change (expressed as a percentage of fs counts) versus counter gate time.
Frequency to Voltage Conversion

The VFC110 can also be connected as a frequency-to-voltage converter (Figure 4). The input frequency pulse is applied to the comparator input. Negative-going pulses across 0V trigger reference current pulses averaged by the integrator op amp. The values of the primary capacitor and feedback resistor (same as RIN) are determined according to Table 1. Input frequency pulses must not remain negative for more than the duration of one pulse period. Figure 4 shows the time required to ensure this. If the negative input frequency pulses are of longer duration, the capacitive coupling circuit shown can be used. Level shifting or capacitively coupled circuits should not provide pulses below -5V, as this may damage the comparator inputs.
This frequency-to-voltage converter works by averaging (filtering) the reference current pulses triggered on each falling edge of the frequency input. A voltage ripple with a frequency equal to the input will appear in the output voltage. The magnitude of this ripple voltage is inversely proportional to the integrator capacitance. Ripple can be made arbitrarily small with large capacitors at the expense of settling time. The RC time constants of CINT and RIN determine the settlement behavior. A better compromise between output ripple and settling time can be achieved by adding a low-pass filter after the voltage output.