General Instructions

The adsp-bf531/adsp-bf532/adsp-bf533 processors are part of the blackfin family of products and integrate the Analog Devices/Intel Micro Signal Architecture (msa). The Blackfin processor combines the advantages of dual-Mac state-of-the-art signal processing engines, clean, quadrature risclike microprocessor instruction sets, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

The adsp-bf531/adsp-bf532/adsp-bf533 processors are fully code and pin compatible, differing only in performance and on-chip memory. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal processing in an integrated package.

Portable Low Power Architecture

Blackfin processors provide world-class power management and performance. The blackfin processor adopts a low-power and low-voltage design approach, with dynamic power management capabilities that can vary voltage and operating frequency, significantly reducing overall power consumption. Changing the voltage and frequency can significantly reduce power consumption compared to just changing the operating frequency. This means longer battery life for portable devices.

system integration

The adsp-bf531/adsp-bf532/adsp-bf533 processors are highly integrated system-on-chip solutions for next-generation digital communications and consumer multimedia applications. By combining industry-standard interfaces with high-performance signal processing cores, users can rapidly develop cost-effective solutions without the need for expensive external components. System peripherals include a uart port, a spi port, two serial ports (sports), four general-purpose timers (three with pwm capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

Processor Peripherals

adsp-bf531/adsp-bf532/adsp-bf533 processors - a rich set of peripherals connected to the core via multiple high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see diagram on page 1 functional block diagram in 1). General purpose peripherals include uarts, timers with pwm (pulse width modulation) and pulse measurement capabilities, general purpose I/O pins, real-time clock and watchdog timer functions. This set of functions addresses a variety of typical system support needs and is enhanced by system scalability through components. In addition to these general purpose peripherals, the processor contains high-speed serial and parallel ports for interfacing with various audio, video and modem codec functions; an interrupt controller for flexible management of interrupts from on-chip peripherals or external sources ; and performance and power characteristics for customizing processors and systems for many application scenarios. With the exception of general purpose I/O, real-time clock and timers, all peripherals are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor's various memory spaces, including external sdram and asynchronous memory. Multiple on-chip buses running at frequencies up to 133MHz provide enough bandwidth to keep the processor core running with all on-chip and external peripheral activity.

These processors include an on-chip voltage regulator that supports the processor's dynamic power management capabilities. The voltage regulator provides a range of core voltage levels for VDDEXT. The voltage regulator can be bypassed at the user's discretion.

Blackfin processor core

As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computational unit processes 8-bit, 16-bit or 32-bit data from the register file.

The computational register file contains eight 32-bit registers. When performing computational operations on 16-bit operand data, the register file operates as 16 separate 16-bit registers. All operands for computation operations come from the multiport register file and instruction constant fields.

Each mac can perform a 16-bit by 16-bit multiplication per cycle, accumulating the result into a 40-bit accumulator. Signed and unsigned formats, rounding, and saturation are supported. The ALU performs a traditional set of arithmetic and logic operations on 16-bit or 32-bit data. In addition, a number of special instructions are included to accelerate various signal processing tasks. These operations include bit operations such as field extraction and overall count, modulo 232 multiplication, division primitives, saturation and rounding, and sign/exponent detection. The video instruction set includes byte alignment and packing operations, 16-bit and 8-bit addition with clipping, 8-bit average operations, and 8-bit subtract/absolute/accumulate (saa) operations. Compare/select and vector search instructions are also provided.

For some instructions, two 16-bit alu operations can be performed simultaneously on a register pair (16-bit high half and 16-bit low half of the compute register). Four 16-bit operations can be performed using the second ALU.

A 40-bit shifter can perform shifts and rotations, and is used to support normalization, field extraction, and field storage instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, Sequencer supports PC-relative and indirect conditional jumps (with static branch prediction) and subroutine calls. Hardware is provided to support zero-overhead loops. The architecture is fully interlocked, which means that programmers do not need to manage pipes when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multi-port register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering) and eight additional 32-bit pointer registers (for C-type index stack operations).

The blackfin processor supports an improved Harvard architecture and a hierarchical memory structure. Level 1 (l1) memory typically runs at full processor speed with little or no latency. At level l1, the instruction memory only holds instructions. Two data memories hold data, and a dedicated scratch line data memory stores stack and local variable information.

In addition, multiple L1 memory blocks are provided, providing a configurable combination of SRAM and cache. The memory management unit (mmu) provides memory protection for individual tasks that may be running on the core, and can protect system registers from accidental access.

The architecture provides three modes of operation: user mode, management mode, and emulation mode. User mode provides a protected software environment by restricting access to certain system resources, while admin mode has unrestricted access to system and core resources.

The blackfin processor instruction set has been optimized so that the 16-bit opcodes represent the most commonly used instructions, resulting in excellent compiled code density. Complex dsp instructions are encoded into 32-bit opcodes representing full-featured multifunction instructions. The blackfin processor supports limited multi-issue capability, where 32-bit instructions can be issued in parallel with two 16-bit instructions, allowing programmers to use many core resources in a single instruction cycle.

The blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use with C/C++ compilers, resulting in fast and efficient software implementations.

memory structure

The adsp-bf531/adsp-bf532/adsp-bf533 processors use 32-bit addresses to treat memory as a single unified 4Gbyte address space. All resources, including internal memory, external memory, and I/O control registers, occupy a separate portion of this common address space. The memory portion of this address space is arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory (such as cache or sram) and larger, lower cost and performance off-chip memory systems.

The l1 memory system is the primary highest performance memory available to blackfin processors. The off-chip memory system accessed through the External Bus Interface Unit (EBIU) provides sdram, flash and sram expansion, optionally accessing up to 132M bytes of physical memory.

The memory dma controller provides high bandwidth data movement capabilities. It can perform block transfers of code or data between internal memory and external memory spaces.

Internal (on-chip) memory

The processor has three on-chip memories that provide high-bandwidth access to the core.

The first block is the l1 instruction memory, consisting of up to 80k bytes of sram, of which 16k bytes can be configured as a four-way set associative cache. This memory is accessed at the maximum speed of the processor.

The second on-chip memory block is l1 data memory, consisting of one or two columns of up to 32k bytes. The memory bank is configurable and provides caching and sram functionality. This block of memory is accessed at full processor speed.

The third memory block is a 4k byte scratchpad sram, which runs at the same speed as l1 memory, but can only be accessed as data sram and cannot be configured as a cache.

External (off-chip) memory

External memory is accessed through the External Bus Interface Unit (EBIU). This 16-bit interface provides glue-free connections to synchronous DRAM (sdram) as well as up to four asynchronous storage devices including flash, eprom, rom, sram, and memory-mapped i/o devices.

The PC133 compatible SDRAM controller can be programmed to interface up to 128Mbytes of SDRAM. The sdram controller allows each internal sdram bank to open one row, up to four internal sdram banks, thus improving the overall performance of the system.

The asynchronous memory controller can be programmed to control up to four sets of devices, with very flexible timing parameters for a wide variety of devices. Regardless of the size of the device used, each storage group occupies a 1-megabyte segment, so the storage groups are only contiguous if each is filled with 1-megabyte of memory.

I/O memory space

Blackfin processors do not define a separate I/O space. All resources are mapped through a flat 32-bit address space. On-chip I/O devices map their control registers to memory-mapped registers (MMRs) at addresses near the top of the 4Gbyte address space. They are divided into two smaller blocks, one contains the control mmr for all core functions and the other contains the registers needed to set up and control the peripherals on the chip external to the core. mmr is only accessible in supervisor mode and appears as reserved space for on-chip peripherals.

guide

The adsp-bf531/adsp-bf532/adsp-bf533 processors contain a small boot kernel that configures the appropriate peripherals for booting. If the processor is configured to boot from the boot ROM memory space, the processor begins executing from the on-chip boot ROM.

event handling

The event controller on the handler handles all asynchronous and synchronous events to the handler. The adsp-bf531/adsp-bf532/adsp-bf533 processors provide event handling that supports nesting and prioritization. Nesting allows multiple event service routines to be active at the same time. Prioritization ensures that the service of high-priority events takes precedence over the service of low-priority events. The controller supports five different types of events: (1) Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface. (2), reset - this event resets the processor. (3), Non-Maskable Interrupt (NMI) – NMI events can be generated to the processor by a software watchdog timer or an NMI input signal. NMI events are often used as power outage indicators to initiate an orderly shutdown of the system. (4), Exception – an event that occurs synchronously with program flow (ie, an exception occurs before an instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. (5) Interrupt - an event that occurs asynchronously with the program flow. They are caused by input pins, timers and other peripherals, and explicit software instructions. Each event type has an associated register to hold the return address and an associated event instruction return. When an event is fired, the state of the processor is saved in the manager stack.

The event controller of the adsp-bf531/adsp-bf532/adsp-bf533 processors consists of two levels: the core event controller (cec) and the system interrupt controller (sic). The core event controller works in conjunction with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from peripherals go into the sic, which are then routed directly to the general interrupts of the cec.

Core Event Controller (CEC)

In addition to dedicated interrupts and exception events, CEC supports 9 general purpose interrupts (IVG15–7). Of these general purpose interrupts, it is recommended to reserve the two lowest priority interrupts (ivg15-14) for software interrupt handlers, leaving 7 priority interrupt inputs to support the processor's peripherals. Table 2 describes the inputs to CEC, identifying their names in the event vector table (EVT) and listing their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides event mapping and routing from many peripheral interrupt sources to the CEC's priority generic interrupt inputs. Although the processor provides a default mapping, the user can change the mapping and priority of interrupt events by writing the appropriate values to the Interrupt Assignment Register (sic_iarx). Table 3 describes the input to SIC and the default mapping to CEC.

event control

Handlers provide a very flexible mechanism to control the handling of events. In cec, three registers are used to coordinate and control events. Each register is 32 bits wide: (1), CEC Interrupt Latch Register (ILAT) – The ILAT register indicates the time the event is latched. The appropriate bits are set when the processor locks the event and cleared when the event is accepted by the system. This register is automatically updated by the controller, but can also be written to clear (un)lock a lock event. This register can be read in supervisor mode and can only be written in supervisor mode when the corresponding imask bit is cleared. (2), CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of a single event. When a bit is set in the imask register, the event is unmasked and handled by cec when asserted. A clear bit in the imask register masks the event, preventing the processor from handling the event, even though the event might be latched in the ilat register. This register can be read or written in supervisor mode. Note that general purpose interrupts can be globally enabled and disabled using the sti and cli directives respectively. (3), CEC Interrupt Pending Register (IPEND) – The IPEND register tracks all nested events. A set bit in the IPEND register indicates that the event is currently active or nested at some level. This register is automatically updated by the controller, but can be read in supervisor mode.

The SIC further controls event handling by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each peripheral interrupt event shown in Table 3.

(1), SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in this register, this peripheral event is unmasked and handled by the system when asserted. A clear bit in this register masks a peripheral event, preventing the processor from processing the event.

(2), SIC Interrupt Status Register (SIC_ISR) – Since multiple peripherals can be mapped to a single event, this register allows software to determine the source of the peripheral event that triggered the interrupt. A set bit indicates that the peripheral is asserting an interrupt, and a cleared bit indicates that the peripheral is not asserting an event.

(3) SIC Interrupt Wake-Up Enable Register (SIC_iwr) – By enabling the corresponding bits in this register, a peripheral can be configured to wake up the processor if the core is idle when the event is generated. See Dynamic Power Management on page 11.

Since multiple interrupt sources can be mapped to a common interrupt, multiple pulses of interrupt events that have been detected on this interrupt input can be asserted simultaneously before or during interrupt processing. As an interrupt acknowledgement, the sic monitors the contents of the ipend register.

When an interrupt rising edge is detected, the appropriate ILAT register bits are set (detection takes two core clock cycles). This bit is cleared when the corresponding ipend register bit is set. The IPEND bit indicates that the event has entered the processor pipeline. At this point, the cec recognizes and queues the next rising edge event on the corresponding event input. The minimum latency transition from the rising edge of a general interrupt to the asserted ipend output is three core clock cycles; however, the latency can be much higher, depending on the activity and state inside the processor.

DMA controller

The adsp-bf531/adsp-bf532/adsp-bf533 processors have multiple independent DMA channels and support automatic data transfer with minimal processor core overhead. DMA transfers can occur between the processor's internal memory and any DMA-capable peripheral. Additionally, DMA transfers can be done between any DMA-capable peripheral and an external device connected to an external memory interface, including sdram controllers and asynchronous memory controllers. Peripherals that support DMA include sports, spi port, uart and ppi. Every dma capable peripheral has at least one dedicated dma channel.

The dma controller supports one-dimensional (1-d) and two-dimensional (2-d) dma transmission. DMA transfer initialization can be implemented from registers or parameter sets called descriptor blocks.

The 2D dma function supports arbitrary row and column sizes (up to 64k elements by 64k elements), arbitrary row and column steps (up to ±32k elements). Furthermore, the column step size can be smaller than the row step size, allowing for interleaved data flow. This feature is especially useful in video applications where data can be deinterleaved on the fly.

Examples of DMA types supported by the DMA controller include: (1), a single linear buffer that stops when done. (2) A circular, auto-refreshed buffer that interrupts each full or partially full buffer. (3) 1-D or 2-D DMA using descriptor linked list. (4) Use the two-dimensional DMA of the descriptor array, and only specify the basic DMA address in the public page.

In addition to the dedicated peripheral dma channels, there are two pairs of memory dma channels for transfers between the various memories of the processor system. This allows minimal processor intervention to transfer blocks of data between any memory, including external sdram, rom, sram, and flash memory. Memory DMA transfers can be controlled through a very flexible descriptor-based approach or standard register-based automatic buffering mechanisms.

Real Time Clock

The processor Real Time Clock (RTC) provides a powerful set of digital watch functions including current time, stopwatch and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The RTC peripheral has dedicated power pins so it can stay powered up and clocked even when the rest of the processor is in a low power state. The RTC offers a variety of programmable interrupt options, including interrupts per second, minutes, hours, or day clock timing, programmable stopwatch countdown interrupts, or interrupts at programmed alarm times.

The input clock frequency of 32.768khz is divided into 1hz signal by the prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32768-day counter.

When enabled, the alarm function generates an interrupt when the timer output matches the programmed value in the alarm control register. The two alarms are time of day and time of day.

The stopwatch function counts down from the programmed value with a resolution of 1 second. An interrupt is generated when the stopwatch is enabled and the counter underflows. Like other peripherals, the RTC can wake the processor from sleep mode when any RTC wakeup event is generated. In addition, the rtc wake-up event can wake up the processor from deep sleep mode and wake up the on-chip voltage regulator from power-down state.

Connect the RTC pins RTXi and RTXo with external components as shown in Figure 6.

Recommended components:

X1 = Zodiac EC38J (Through Hole Assembly) or Epson MC405 12 pf Load (Surface Mount Assembly)

C1 = 22 PF; C2 = 22 PF; R1 = 10 meters:

Note: c1 and c2 are crystals designated for x1.

Please contact the crystal manufacturer for details. The C1 and C2 specifications assume a board tracking capacitance of 3pF.

watchdog timer

adsp-bf531/adsp-bf532/adsp-bf533 processors. A 32-bit timer is included that can be used to implement a software watchdog function. If the timer expires before being reset by software, a software watchdog can increase system availability by generating a hardware reset, non-maskable interrupt (nmi), or general purpose interrupt to force the processor into a known state. The programmer initializes the count value of the timer, enables the appropriate interrupt, and then enables the timer. After this, software must reload the counter before it counts from the programmed value to zero. This protects the system from an unknown state where the software that normally resets the timer stops functioning due to external noise conditions or software bugs.

If configured to generate a hardware reset, the watchdog timer will reset the core and processor peripherals. After reset, software can determine if the watchdog was the source of the hardware reset by interrogating the status bits in the watchdog timer control register. The timer is clocked by the system clock (SCLK) at the maximum frequency FSCLK.

timer

There are four general-purpose programmable timer units in the adsp-bf531/adsp-bf532/adsp-bf533 processors. The three timers have an external pin that can be configured as a pulse width modulator (pwm) or timer output, as an input to the timer clock, or as a mechanism for measuring pulse width and external event period. These timers can be synchronized with an external clock input to the pf1 pin (taclk), an external clock input to the ppi clock pin (tmrclk), or to the internal sclk. The timer unit can be used with the uart to measure the width of the pulses in the data stream to provide automatic tone detection for the serial channel. Timers can generate interrupts to the processor core, provide periodic events for synchronization, either to the system clock or to count external signals.

In addition to the three general-purpose programmable timers, a fourth timer is provided. This additional timer is clocked by the internal processor clock and is typically used as the system clock to generate periodic interrupts to the operating system.

Serial port (sport)

The adsp-bf531/adsp-bf532/adsp-bf533 processors contain two dual-channel synchronous serial ports (sport0 and sport1) for serial and multiprocessor communication. Motion supports the following features:

(1), can carry out I2s operation.

(2) Two-way operation - each sport has two independent sets of transmit and receive pins, supporting eight I2s stereo audio channels.

(3), buffered (8 deep) transmit and receive ports - each port has a data register for transferring data words between other processor components and a shift register for shifting data in and out Shift out of the data register.

(4) Clock - Each transmit and receive port can use an external serial clock or generate its own clock with a frequency range from (fsclk/131070) Hz to (fsclk/2) Hz.

(5), word length – each movement supports serial data words from 3 bits to 32 bits in length, with the most significant or least significant bit transmitted first.

(6), frame - each transmit and receive port can operate, each data word with or without frame synchronization signal. The frame sync signal can be generated internally or externally, high or low, with two pulse widths and early or late frame sync.

(7), hardware companding - according to ITU recommendation G.711, each movement can perform A-law or μ-law companding. Companding can be selected on moving transmit and/or receive channels without additional delay.

(8) DMA operation with single-cycle overhead – each movement can automatically receive and transfer multiple memory data buffers. Processors can chain or chain motion and DMA transfer sequences between memory.

(9) Interrupts - Each transmit and receive port generates an interrupt upon completion of a data word transfer, or after transferring one or more data buffers via DMA.

(10), Multi-channel capability - Each sport supports 128 channels in a 1024-channel window, and is compatible with H.100, H.110, MVIP-90 and HMVIP standards. An additional 250 mV of motion input hysteresis can be enabled by setting Bit 15 of the PLL control register. When this bit is set, the hysteresis of all motion input pins is increased.

Serial Peripheral Interface (SPI) port

The adsp-bf531/adsp-bf532/adsp-bf533 processors have spi-compatible ports that enable the processor to communicate with multiple spi-compatible devices.

The SPI interface uses three pins to transfer data: two data pins (Master Out Slave In, MOSI and Master In Slave Out, MISO) and one clock pin (Serial Clock, sck). The SPI chip select input pin (spiss) lets other spi devices select process-sor and the seven spi chip select output pins (spisel7–1) let the processor select other spi devices. The SPI select pins are general purpose I/O pins for reconfiguration. Using these pins, the spi port provides a full-duplex, synchronous serial interface that supports master/slave mode and multi-master environments.

The baud rate and clock phase/polarity of the SPI port is programmable, and it has an integrated DMA controller that can be configured to support transmit or receive data streams. The spi-dma controller can only service one-way access at any given time.

The spi port clock rate is calculated as follows:

where the 16-bit spi_baud register contains values from 2 to 65535.

During transmission, the spi port sends and receives data simultaneously by shifting data in and out serially on its two serial data lines. The serial clock line synchronizes data shifting and sampling on the two serial data lines.

UART port

The adsp-bf531/adsp-bf532/adsp-bf533 processors provide full-duplex universal asynchronous transceiver (uart) ports, which are fully compatible with the pc standard uart. The UART port provides a simplified UART interface for other peripherals or hosts, supports full duplex, supports DMA, and asynchronous serial data transfer. The UART port supports 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and no parity. The UART port supports two modes of operation:

(1), PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UART registers. Data is double-buffered both when sent and received.

(2), DMA (Direct Memory Access) – DMA controller transfers send and receive data. This reduces the number and frequency of interrupts required to transfer data between memories. The UART has two dedicated DMA channels, one for transmit and one for receive. These dma channels have a lower default priority than most dma channels because of their relatively low service rates.

The baud rate, serial data format, error code generation and status, and interrupts for the UART port are all programmable. The UART programmable functions include: (1), supports bit rates from (fsclk/1048576) bits/sec to (fsclk/16) bits/sec. (2), support data format from 7 bits to 12 bits per frame. (3) Both send and receive operations can be configured to generate maskable interrupts to the processor.

The clock rate of the UART port is calculated as follows:

where the 16-bit uart_ divisor comes from the uart_dlh register (most significant 8 bits) and the uart_dll register (least significant 8 bits). Combined with the general timer function, it supports automatic audio detection. The functionality of uart is further extended with support for the Infrared Data Association (IRDA) Serial Infrared Physical Layer Link Specification (SIR) protocol.

General purpose I/O port F

The adsp-bf531/adsp-bf532/adsp-bf533 processors have 16 bidirectional general purpose I/O pins on port F (PF15–0). Each general purpose I/O pin can be individually controlled by manipulating the GPIO control, status and interrupt registers:

(1), GPIO direction control register - specifies the direction of each individual PFX pin as input or output.

(2), GPIO control and status registers - the processor adopts a "write-modify" mechanism that allows any combination of a single GPIO pin to be modified in a single instruction without affecting the level of any other GPIO pins. Four control registers are provided. Write a register to set a GPIO pin value, write a register to clear a GPIO pin value, write a register to toggle a GPIO pin value, write a register to specify a GPIO pin value. Reading the GPIO status register allows software to interrogate the meaning of the GPIO pins.

(3) GPIO interrupt mask register - Two GPIO interrupt mask registers allow each individual PFX pin to be used as an interrupt for the processor. Similar to the two GPIO control registers used to set and clear individual GPIO pin values, one GPIO interrupt mask register sets bits to enable interrupt functionality and the other GPIO interrupt mask register clears bits to disable interrupt functionality. Pfx pins defined as inputs can be configured to generate hardware interrupts, while pfx pins defined as outputs can be triggered by software interrupts.

(4), GPIO interrupt-sensitive registers - two GPIO interrupt-sensitive registers specify whether a single PFX pin is level-sensitive or edge-sensitive, and whether edge-sensitive is only the rising edge of the signal or both rising and falling edges are important. One register selects the type of sensitivity, and one register selects which edges are important for edge sensitivity.

Parallel Peripheral Interface

The processor provides a parallel peripheral interface (ppi) that can connect directly to parallel ADCs and DACs, video encoders and decoders, and other general-purpose peripherals. ppi consists of a dedicated input clock pin, up to three frame sync pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate, and synchronization signals can be configured as inputs or outputs.

ppi supports multiple general purpose and itu-r 656 modes of operation. In general mode, ppi provides half-duplex bidirectional data transfer of up to 16 bits of data. Up to three frame sync signals are also provided. In itu-r 656 mode, ppi provides half-duplex bidirectional transmission of 8-bit or 10-bit video data. In addition, on-chip decoding of embedded start of line (sol) and start of field (sof) preamble packets is supported.

General Mode Description

ppi's generic mode is designed to accommodate a wide variety of data capture and transfer applications. Three different sub-modes are supported: (1), Input Mode - Frame Sync and Data Input to PPI. (2), frame capture mode – frame synchronization is the output of the PPI, but the data is the input. (3), output mode – frame synchronization and data are output from PPI.

Input

Input mode is used for ADC applications, and video communication with hardware signaling. In its simplest form, ppi_fs1 is an external frame sync input that controls when data is read. ppi_delay mmr allows the delay (in ppi_clk cycles) between receiving this frame sync and initiating a data read. The number of input data samples is user programmable and defined by the contents of the ppi count register. PPI supports 8-bit and 10-bit to 16-bit data, programmable in the PPI_Control register.

frame capture mode

Frame capture mode allows the video source to act as a slave (for example, for frame capture). The processor controls when the video source is read. ppi_fs1 is the hsync output and ppi_fs2 is the vsync output.

output mode

The output mode is used to transmit video or other data, and up to three output frames are synchronized. Typically, single-frame sync is suitable for data converter applications, while two- or three-frame sync can be used to send video via hardware signaling.

ITU-R 656 mode description

PPI's itu-r 656 mode is designed to accommodate a wide variety of video capture, processing and transmission applications. Three different sub-modes are supported: (1), active video mode only; (2), vertical blanking mode only; (3), full field mode

Active video only mode

Use Active Video Only mode only when the active video portion of the field and not any blanking interval is of interest. The ppi does not read any data between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking interval. In this mode, control byte sequences are not stored into memory; they are filtered by ppi. After syncing to the beginning of field 1, ppi will ignore incoming samples until it sees the sav code. The user specifies the number of active video lines per frame (in the PPI count register).

Vertical Blanking Interval Mode

In this mode, the PPI only transmits vertical blanking interval (VBI) data.

full field mode

In this mode, the entire incoming bitstream is read via ppi. This includes active video, control preamble sequences, and ancillary data that can be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization with field 1. Data is automatically transferred from the processor core to and from the isochronous channel through 8 DMA engines.

Dynamic Power Management

The adsp-bf531/adsp-bf532/adsp-bf533 processors offer four operating modes, each with different performance/power profiles. In addition, dynamic power management provides control to dynamically change the processor core supply voltage, further reducing power consumption. Controlling the clocks of each processor peripheral also reduces power consumption. Summary of power settings for each mode.

Full open working mode for maximum performance

In full-on mode, the PLL is enabled and not bypassed, providing maximum operating frequency capability. This is the power-up default execution state for maximum performance. The processor core and all enabled peripherals run at full speed.

Moderate energy saving in active operation mode

In active mode, the PLL is enabled but bypassed. Since the pll is bypassed, the processor's core clock (cclk) and system clock (sclk) run at the frequency of the input clock (clkin). DMA access is available for properly configured l1 memory.

In active mode, the PLL can be disabled through the PLL Control Register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to fully on or sleep mode.

High dynamic energy saving in sleep mode

Sleep mode reduces dynamic power consumption by disabling the processor core's clock (cclk). However, the pll and system clock (sclk) continue to work in this mode. Usually, an external event or rtc activity wakes up the processor. When in sleep mode, the wake-up assertion causes the processor to detect the value of the bypass bit in the PLL Control Register (PLL_CTL). If bypass is disabled, the processor will transition to fully on mode. If bypass is enabled, the processor will transition to active mode. In sleep mode, system DMA access to L1 memory is not supported.

Deep-sleep operating mode for maximum dynamic power savings

Deep-sleep mode maximizes dynamic power savings by disabling clocks to the processor core (CCLK) and all synchronous peripherals (SCLK). Asynchronous peripherals (like rtc) may still be running, but cannot access internal resources or external memory. This power-down mode can only be exited by asserting a reset interrupt (reset) or an asynchronous interrupt generated by the rtc. When in deep sleep mode, rtc async interrupt causes process - or transition to active mode. Asserting a reset in deep sleep mode causes the processor to transition to fullon mode.

Maximum Static Power Savings in Sleep State

The sleep state maximizes static power savings by disabling voltages and clocks to the processor core (CCLK) and all synchronous peripherals (SCLK). The processor's internal voltage regulator can be turned off by writing b 00 to the frequency bits of the vr ctl register. In addition to disabling the clocks, the internal supply voltage (VDDINT) is set to 0 V to provide the lowest static power consumption. If the processor state is to be preserved, any internally stored critical information (memory contents, register contents, etc.) must be written to a non-volatile storage device before power is removed. Since VDDEXT is still available in this mode, all external pins are tri-stated unless otherwise specified. This allows other devices that can be connected to the processor to still be powered without drawing unnecessary current. The internal power regulator can be woken up by the real-time clock, wake-up or assert the reset pin.

power saving

The processor supports three different power domains. The use of multiple power domains maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the processor's internal logic into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for different power domains.

The power consumed by the processor is largely a function of the processor clock frequency and the square of the operating voltage. For example, a 25% reduction in clock frequency reduces dynamic power consumption by 25%, while a 25% reduction in voltage reduces dynamic power consumption by more than 40%. Furthermore, these power savings are additive because power savings can be significant if both clock frequency and supply voltage are reduced.

The processor's dynamic power management feature allows dynamic control of the processor's input voltage (vddint) and clock frequency (fcclk). Power savings can be modeled using power savings factor and power savings percentage calculations.

The power saving factor is calculated as follows:

The variables in the formula are:

FCK is the nominal core clock frequency fcclkred is the reduced core clock frequency vddinom is the nominal internal supply voltage

Has the internal supply voltage of Wident dropped?

TNF is the duration of the run at fcclknom tred is the duration of the run at fcclkred The percentage of power saving is calculated as: % power saving = – power saving factor 1 100%

Voltage regulation

The blackfin processor provides an on-chip voltage regulator that generates the appropriate vddint voltage levels from the vddext supply. See Operating Conditions on page 20 for model specific regulator tolerances and acceptable VDDEXT ranges.

Figure 7 shows the typical external components required to complete a power management system. The regulator controls the internal logic voltage levels and is programmable in 50 mV increments through the Voltage Regulator Control Register (vr_ctl). To reduce standby power consumption, the internal voltage regulator can be programmed to cut power to the processor core while maintaining the I/O power supply (VDDEXT). When sleeping, I/O power is still in use, so no external buffers are required. The voltage regulator can be woken up by RTC or reset by asserting, both of which initiate a start-up sequence. Users can also disable and bypass the regulator at their discretion.

Voltage Regulator Layout Guidelines

Regulator external component placement, board routing, and bypass capacitors all have a significant impact on the noise injected into other analog circuits on the chip. During board layout, the VROUT1–0 traces and voltage regulator external components should be considered noise sources and should not be routed or placed near sensitive circuits or components on the board. All internal and I/O power supplies should be bypassed, and the bypass capacitors should be as close to the processor as possible.

clock signal

The adsp-bf531/adsp-bf532/adsp-bf533 processors can be clocked by an external crystal, a sine wave input, or a buffered shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not stop, change or run below the specified frequency during normal operation. This signal is connected to the clkin pin of the processor. When using an external clock, the external pins must be left unconnected. Alternatively, since the processor includes an on-chip oscillator circuit, an external crystal can be used. For fundamental frequency operation, use the circuit shown in Figure 8.

A parallel resonant, fundamental frequency, microprocessor-grade crystal is connected to the clkin and xtal pins. The on-chip resistance between the CLKIN and XTAL pins is in the range of 500 K. Further paralleling of resistors is generally not recommended. The two capacitors and series resistor shown in Figure 8 trim the phase and amplitude of the sinusoidal frequency. The capacitor and resistor values shown in Figure 8 are typical values only. Capacitance values depend on the crystal manufacturer's load capacitance recommendations and physical PCB layout. The resistor value depends on the drive level specified by the crystal manufacturer. System design should validate custom values based on careful investigation of multiple devices that exceed the allowable temperature range.

The third overtone crystal can be used at frequencies above 25 MHz. Then, as shown in Figure 8, the circuit is modified by adding a tuned inductive circuit to ensure that the crystal operates only at the third overtone.

As shown in Figure 9, the core clock (cclk) and the system peripheral clock (sclk) are derived from the input clock (clkin) signal. The on-chip pll is capable of multiplying the clkin signal by a user-programmable multiplication factor of 0.5 to 64 (bounded by a specified minimum and maximum VCO frequency). The default multiplier is 10, but can be modified by a sequence of software instructions. Real-time frequency changes can be achieved by simply writing to the pll_div register.