Features

● Maximum conversion time 20μs

● Single+5V power operation

● Compatible with 16 -bit ADS7813

● Easy to use string Ring interface

● 0.3 ""DIP-16 and SO-16

● ± 0.5LSB maximum entrance and DNL

● minimum signal ratio 72db

● Use internal or external reference

● Multiple input range

● 35MW maximum power consumption

● No missing code

● 50μW power off mode [123 ]

Application

● Data acquisition system

● Industrial control

● Test equipment

● Digital signal processing

Instructions

ADS7812 is a low power consumption, single+5V power supply, 12 -bit sampling modulus converter. It contains a complete 12 -bit capacitor SAR A/D, with sampling/maintenance, clock, benchmark, benchmark And serial data interface.

The converter can be configured to various input range, including ± 10V, ± 5V, 0V to 10V and 0.5V to 4.5V. It can also provide high impedance 0.3V to 2.8V inputs. Scope (input impedance gt; 10m ). For most input range, the input voltage can be swinged to+16.5V or -16.5V without damaging the converter. The interface allows data to synchronize with internal or external clocks. ADS7812 is specified at a temperature sampling rate of 40kHz within the temperature range of -40 ° C to+85 ° C. It can provide 0.3-inch DIP-16 or SO-16 packaging.

[

[ 123]

Note: (1) The actual value may change ± 30%.

Typical performance curve

Unless otherwise explained, under the+5V input,+5V , u003d+5V input.

Basic operation Internal data clock

Figure 1A shows ± ± The basic circuit of ADS7812 is operated within 10V input range. To start the result of conversion and serial transmission, it must provide a decrease edge for CONV input. ""Busy"" will turn low, indicating that the conversion has begun, and it will remain low until the conversion is complete. . During the conversion process, the result of the last conversion will be transmitted through data, and DataCLK provides a synchronous clock for serial data. The 12 -bit of MSB is a binary complement codeFormat. Each data is busy in the data clock busy in the entire serial transmission process, which can be used as frame synchronous signals.

External data clock

FIG. 1B shows the basic circuit of ADS7812 in the ± 10V input range. To start the conversion, you must provide a decrease edge for CONV input. ""Busy"" will become low, indicating that the conversion has begun and will remain low until the conversion is completed. Before the conversion is close to the end, the internal working register that saves the conversion result will be transmitted to the internal shift register.

Internal displacement registers enter the clock via datalk. The recommendation method of reading the conversion result is to provide a serial clock after the conversion is completed. For more information, see the external data CLK in the data table of this data table.

Start conversion

If the conversion is not current Keep it in the maintenance mode and start the conversion, as shown in Figure 2, the time is shown in Table II. During the conversion, the CONV input was ignored. Starting conversion does not depend on CS. The conversion can be started once every 25 μs (maximum conversion rate of 40kHz). There is no minimum conversion rate.

Even if the CONV input is ignored during the conversion process, the input should be kept static during the conversion period. The conversion on this number input can easily be coupled to the sensitive simulation part of the converter, which has a adverse effect on the conversion result (more information about the external digital signal sensitivity part of this data table).

Ideally, the conv input has a low response and keeps low in the entire conversion process. It should return to the high position at some point after busy. In addition, before the next conversion starts, it should be high, within the shortest time period given by T5. This will ensure that the number conversion on the CONV input will not affect the signal obtained by the next conversion.

The acceptable alternative method is to return the CONV input high level as soon as possible after the conversion starts. For example, a 100ns wide negative pulse can generate a good CONV input signal. It is strongly recommended to rise from T2 to Busy after the start of the conversion. Conv input should keep static (high or low). During this period, the converter is more sensitive to external noise.

Reading data

The digital output of ADS7812 adopted adoption Binary binary composite (BTC) format. Table 3 shows the relationship between digital output words and analog input voltage under the ideal conditions.

FIGThe relationship between output and internal logic.

FIG. 4 shows when to update the internal shift register of ADS7812, and the relationship with a single conversion cycle. These two pictures together pointed out a very important aspect of ADS7812: before the conversion is completed, the conversion result is unavailable. The following sections will be discussed.

Internal data clock

In the case of low EXT/int connection, the result of the transition ""n"" is transmitted serially during the ""n+1"" period, as shown in Figure 5, time, time As shown in Table II. The serial transmission of data occurs only during the conversion process. When the transmission is not performed, Data and DataCLK are low.

During the conversion process, the previous conversion results will be transmitted through data, and DataCLK provides a synchronous clock for serial data. The data format is 12 bits. The complement code of binary 2 and MSB First, each person's data is effective at the rising and down edge of the DataCLK. During the entire serial transmission task, the busyness is low and can be used as frame synchronous signals.

External data clock

When EXT/INT is at a high level, the result of the conversion ""n"" is transformed after the conversion, during the next conversion (""n+1"") or the two of them or the two of them Combination time. Figure 6 shows the situation of the conversion result after the conversion is completed. Figure 7 describes the process of reading the results during the next conversion. Figure 8 combines the important aspects of Figure 6 and Figure 7, that is, after the conversion is completed, the results are read, and the rest are read during the next conversion period.

The serial transmission of the conversion result was started by rising edges on DataCLK. The 12 -bit of MSB is a binary complement format. Each data is valid at the decline of DataCLK. In some cases, you can use the rising edge of the DataCLK signal. However, the last one requires an extra clock cycle (not displayed in Figure 6, 7, and 8).

Before the busy rise, the external data clock signal must be low or CS must be high (see T25 in Figure 7 and 8). If this is not observed, the output shift register of the ADS7812 will not update the results with the conversion. Instead, the previous content of the displacement register will be retained, and the new results will be lost.

If you provide more than 12 clock cycles to the DataCLK input, the data output will turn lower after the rising edge of the 13th clock cycle. As long as the timing specification is met, the operation of ADS7812 will not be affected. Before reading the following three paragraphs, please refer to the external digital signal sensitivity of this data. This will explain many issues about how and when to apply external DataCLK signals.

After the conversion, activate the external data clock The preferred method is to provide DataCLK signals before the conversion is completed and the next conversion, as shown in Figure 6. Note that before the next conversion starts, the DataCLK signal should be static. If it is not provided, the DataCLK signal may affect the collected voltage.

Activate external data clocks during the next conversion

Another method of obtaining the transition result is shown in Figure 7. Since the output displacement register will not be updated before the conversion is over, the last result is still valid during the next conversion period. If you can provide fast clock (≥2MHz) to ADS7812, you can read the results during the T2 period. During this period, noise from the DataCLK signal is unlikely to affect the transition result.

During the conversion and the next conversion period, the external data clock is active

FIG Methods. This method is suitable for a microcontroller and slower microcontroller that performs 8 -bit serial transmission. For example, if the fastest serial clock that the microcontroller can produce is 1 μs, and two 8 -bit converters must be used to obtain serial data, the method shown in Figure 6 will cause the throughput (the maximum conversion rate of 26kHz 26kHz To. The method described in Figure 7 cannot be used, because it will violate time T25. The method in FIG. 8 improves throughput (maximum 33kHz, clock is 1 μs), and DataCLK is lower during the T25 period.

The only difference between the compatibility with ADS7813 The only difference between ADS7812 and ADS7813 is the internal control logic and digital interface. Since ADS7813 is a 16 -bit converter, the width of the internal displacement register is 16 bits. In addition, only 16 -bit decisions were made during the conversion process. Therefore, the conversion time of ADS7813 is about 133%of ADS7812.

The time arrangement given in this data table will be compatible with ADS7813 as much as possible. The main concern is the serial clock with different quantities. If the design must be compatible with ADS7812 and ADS7813 at the same time, it is recommended to first consider ADS7813. If the design can be used with ADS7813, it can definitely be used with ADS7812. This is also the same (see the layout of this data table) in terms of layout.

chip selection (CS)

CS input allowed digital output to allow ADS7812 to be disabled, and selected the external DataCLK signal at EXT/int high time. See Figure 9 related to CS -related opening and disable time, and the logic box diagram of ADS7812 is shown in Figure 3. Digital output can be disabled at any time.

Please note that even if the CS is high, the conversion will start at the decrease of CONV. likeIf the EXT/int input is low (internal DataCLK) and the CS is high during the entire conversion process, the previous conversion results will be lost (serial transmission occurs, but data and datals are disabled).

The analog input

ADS7812 provides a variety of input range. This is achieved by connecting the three input resistors to the analog input (VIN), ground (GND) or 2.5V reference buffer output (BUF). Table 1 shows the input range commonly used in data collection applications. These areas are specified to meet the specifications given in the specification table. Table 4 contains a complete list of ideal input range, related input connection, and comments related to the scope.

The input impedance comes from various connections and internal resistance values u200bu200b(refer to the box diagram of the homepage of this data table). The internal resistance value is a typical value, which changes ± 30%due to process changes. However, the ratio of resistance is much better than this. Therefore, the input range will only change a few percentage points between each part, and the change in the input impedance may be as high as ± 30%.

The specification table contains the maximum restrictions of the simulation input range change, but it is only applicable to the scope of the specified offset and gain of the comments field (including all the range listed in Table I). For other scope, no offset and gain are not specified.

Five input range in Table 4 is not recommended for general use. For two of them, the input voltage exceeds the absolute maximum value. As long as the input voltage is kept below the absolute maximum value, these areas can still be used, but this will appropriately significantly reduce the full range of the converter.

The other three input range involved a connection at R2in, which connected to the driver below-0.3V. The input has a reverse ESD to protect the diode ground. If the R2in is below the ground, the diode will be positive bias and the negative input is cut between -0.4V to -0.7V according to the temperature. Here, the full -scale converter of the cost that can still be used.

Note that the voltage at the REF pin is 2.5V. If the internal reference voltage or external reference voltage is 2.5V, this is correct. Other reference voltage will change the value in the table IV.

High impedance mode

When R1in, R2in, and R3IN are connected to analog input, the input range of ADS7812 is 0.3125V to 2.8125V, and the input impedance is greater than 10m This input range can be used to connect ADS7812 directly to various sensors. Figure 10 shows the changes in the impedance of the sensor and the iLe and DLE of ADS7812. The performance of ADS7812 can be improved by allowing more collection timeSensor impedance. For example, for the same iLe/DLE performance, the collection time of 10 μs is about twice the sensor impedance.

The input impedance and capacitors of ADS7812 are very stable with the temperature. The same is true of the sensor. Within the specified temperature range of ADS7812, the graphic changes shown in Figure 10 will be less than a few percent. If the sensor impedance changes greatly with the temperature, the worst case should be used at the worst case.

Drive ADS7812 analog input

In general, any ""quite fast"