2nd v-set when vsg active line and special v-insert

Most CCDs require additional vertical timing during sensor gate lines. When the VSG1 to VSG8 sensor gates are activated, the AD9923A can output a second V group for XV1 to XV13 during line periods. Figure 47 shows a typical vsg line that includes two sets of v-mode groups from v1 to v13. At the beginning of the vsg line, use the appropriate vseqsel register to select the v-mode group. The second v-group is specific to vsg lines and is selected using the vpatsecond register located in the field register. The start of the second vpat group uses the vstartsecond register.

In addition to inserting a second v-pattern in a vsg line, the AD9923a can also insert a second v-pattern in any other single line in each sequence. To enable this feature in a specific sequence, set the spxv_en register to 1 in the corresponding sequence register set. The SPXV_ACT register determines the active line for the special second V mode. The vpatselb and vstartb registers control the v-mode used and the starting pixel position of the special second v-mode.

To avoid undesired behavior, do not use the special second, v-mode in the vsg line; use the existing vpatsecond and vstartsecond registers to insert the second v-mode into the vsg line. It is recommended to use the vpatsecond and vstartsecond registers to create complex timing in the sensor gate lines instead of the groupb registers. Also, given that the special second v-mode insert uses some of the b-group registers, the user cannot use the special second v-mode insert function and the b-group in the same order.

Scan Mode Operation

The AD9923A includes an additional vertical timing mode of operation called scan mode. This mode is used to generate a large number of repetitive pulses across multiple HD lines. Normally, the vertical timing of the AD9923A must be contained within one HD line length, but when scan mode is enabled, HD boundaries are ignored until the region is complete. This is useful, for example, in CCD readout operations. Depending on the vertical resolution of the CCD, up to 3000 clock cycles across several HD line lengths can be required to shift charge out of the vertical interline CCD registers. These registers must be free at the end of the image exposure before image transfer. This can be achieved in scan mode by rapidly transferring out any charge using a series of long pulses output from xv1 to xv13. To enable scan mode in any region, program the corresponding scan register high.

Figure 48 shows an example of scan mode operation. The number of vertical pulses required depends on the vertical resolution of the CCD. The output signals from xv1 to xv13 are generated using v-registers (as shown in Table 15). Create a single pulse using the polarity and toggle position registers. The number of repetitions is then programmed to match the number of vertical shifts required by the CCD. Repeatedly use the vrep register to program in the v-sequence register. This produces a pulse train of the appropriate length. Normally, the burst is truncated at the end of the HD line length, but with scan mode enabled, the HD boundary is ignored. In Figure 48, the scan area occupies 23 high definition lines. After the scan mode area is complete, normal sequence operation resumes in the next area. When using scan mode, use the sequence change position register to set the region boundary to the appropriate row to prevent the scan operation from overlapping with the next V sequence.

Multiplier mode

To generate very wide vertical timing pulses, the vertical regions can be configured as multiplier regions. This mode uses v-type registers in a slightly different way. Multiplier mode can be used to support unusual CCD timing requirements, such as vertical pulses wider than the 13-bit v-switch position counter. Start polarity and toggle position are used in the same way as standard vpat group programming, but the vlen register is used differently. Instead of using a pixel counter (hd counter) to specify switching positions (xvtog1, xvtog2, xvtog3, xvtog4, xvtog5, and xvtog6) in the vpat group, the vlen value is multiplied by the xvtog value to generate very long pulses. To calculate the exact switch position (in pixels after the start position), use the following formula: Multiply mode switch position = xvtog × vlen, because the xvtog value is multiplied by the vlen value, the resolution of the switch position placement is reduced. If vlen=4, the toggle position accuracy will be reduced to 4 pixel steps instead of a single pixel step. How to use vpat bank registers in multiplier mode operation. In multiplied mode, the VREP register should be programmed to the value at the highest toggle position.

The example shown in Figure 49 illustrates this operation. The first toggle position is 2 and the second toggle position is 9. In non-multiplier mode, this causes the v-sequence to switch at pixel 2 and pixel 9 within a single HD row. However, in multiplied mode, the toggle position is multiplied by vlen=4; thus, the first toggle occurs at pixel count=8 and the second toggle occurs at pixel count=36. Scan mode is also enabled to allow switching positions to cross HD line boundaries. Multifunction is only available for signals assigned to Group A. It cannot be used with both sets of functions at the same time, or if any signal is assigned to set B.

Vertical Sensor Door (Shift Door) Mode

In line-to-line CCDs, the vertical sensor gate (VSG) is used to transfer pixel charge from the light-sensitive image area into the light-shielding vertical register. Then, using the xv1 to xv13 vertical transfer pulses and high-speed horizontal clock, the image is read line by line from the light-shielding vertical register.

vsg mode register. The AD9923A has eight VSG outputs, VSG1 to VSG8. Each output can be assigned to one of eight programming modes using the SGPATSEL register. Each pattern is generated in a similar manner to the v-pattern group, with programmable starting polarity (sgpol), first toggle position (sgtog1), and second toggle position (sgtog2). The active line that pulses VSG1 to VSG8 can be programmed using SGactLine1. vsg mode register 1 and sgactline2 register. Additionally, any vsg1 to vsg8 pulses can be individually disabled using the sgmask register. Separate masking allows all sg modes to be preprogrammed and the appropriate pulses can be enabled for each field individually. For maximum flexibility, the sgpatsel, sgmask, and sgactline registers are programmed separately for each field. More details are given in the complete field: Combining v-sequences section.

In addition, there is the sgmask_byp register (address 0x59) to rewrite the sg mask in the field register. The sgmask_byp register allows the sensor gate mask to be changed without modifying the field register value. The sgmask_byp register is updated by sck; therefore, the new sg mask value is updated immediately.

mode register

The mode register is a separate register used to select the field timing of the AD9923A. Typically, all fields, V-sequence, and V-mode group information are programmed into the AD9923A at startup. During operation, the mode register allows the user to select any combination of field timings to meet the current requirements of the system. Using the mode register in conjunction with pre-programmed timing greatly reduces system programming requirements during camera operation. When the camera operating mode is changed, only a small number of register writes are required, rather than having to rewrite the vertical timing information each time the camera mode is changed.

A basic still camera application might require five vertical timing fields, one for draft mode operation, one for autofocus, and three for still image reading. The five fields of register timing information are loaded at startup. Depending on how the camera is used, the mode register selects the field timing that is active during camera operation.

Mode register content VD has been updated

How to use the mode register bits. Unlike other registers, the mode register uses 10 address bits as data bits, increasing the total register size to 38 bits. The addresses msb a11 and a10 are 1 and 0 respectively, which are used to specify the mode register write. The three msbs d37, d36 and d35 are used to specify the number of fields used. Values between 1 and 7 can be selected using these three bits. The remaining register bits are divided into five bit segments to select which programming fields are used and in what order. Up to seven fields can be used in single-mode writes. The AD9923A starts at the field timing specified by the first field bit, switches to the timing specified by the second field bit on the next virtual disk, and so on.

Vertical Timing Example

To better understand how vertical timing can be generated using the AD9923A, consider the example CCD timing diagram in Figure 52. It illustrates a CCD using the general three-field readout technique. As described in Complete Fields: Combining v-sequence sections, each readout field should be divided into separate regions to perform each step of the readout. The Sequence Change Position (SCP) register determines the row boundaries of each region. The vseqsel register then assigns a v-sequence to each region. Each V-sequence contains the specific timing information required for each region: XV1 to XV6 pulses (using VPAT groups), HBLK/CLPOB timing and VSG mode for SG active lines.

The example requires four regions for each of the three fields, labeled Region 0, Region 1, Region 2, and Region 3. Because the AD9923A allows many individual fields to be programmed, Field 0, Field 1, and Field 2 can be created to meet the requirements of this timing example. In this example, the four regions per field are very similar, but the single register per field allows flexibility to accommodate more complex timing requirements.

area 0

Area 0 is a high-speed vertical movement area. Scan mode can be used to generate this timing operation, and the required number of high-speed vertical pulses is used to clear any charge in the CCD vertical registers.

Area 1

Zone 1 consists of two lines and uses standard, single-line, vertical shift timing. The timing of this zone is the same as that of zone 3.

Zone 2

Region 2 is the sensor gate line where the vsg pulses transfer the image to the vertical ccd register. This area may require the use of a second V-group of SG activation lines.

Zone 3

Zone 3 also uses standard, single-line, vertical shift timing, the same timing used in Zone 1. In summary, four fields are required for each of the three fields.

Timing for Region 1 and Region 3 is essentially the same, reducing the complexity of register programming. Other registers must be used during readout operations, such as the mode register, shutter control registers (ie flip-flops and registers that control the outputs of subck, vsub, mshut and strobe) and the afe gain registers vgaain and cdsgain. These registers are described in the Mode Registers and Variable Gain Amplifiers section.

Vertical Drive Signal Configuration

As shown in Figure 53, XV1 to XV13, VSG1 to VSG8, and Xsubck are the outputs of the internal AD9923A timing generator, while v1 to V13 and Subck are the outputs of the AD9923A vertical driver. When vdr_en = high, the vertical driver mixes the xv and vsg pulses and amplifies them to the high voltage needed to drive the ccd. Table 22 to Table 37 describe the output polarity versus input level of these signals. Refer to these tables when determining the register settings for the desired output levels. Note that when vdr_en=low, v1 to v13 are forced to be set to vm and subck to be forced to be set to vll. The VDR_en pin takes precedence over the XV and VSG signals from the timing generator.

shutter timing control

The CCD image exposure time is controlled by the substrate clock signal (subck), which pulses the CCD substrate to clear the accumulated charge. The AD9923A supports three types. Electronic Shutter: Normal, High Precision, Low Speed. The AD9923A is placed with the SubCK pulse to accommodate different readout configurations to further suppress the SubCK pulse during multiple field readout. The AD9923A also provides programmable outputs to control the external mechanical shutter (MSHUT), strobe/flash (strobe), and CCD bias selection signal (VSUB). Up to four regular shutter pulses (shut0 to shut3) and two vsub pulses (vsub0 and vsub1) can be programmed and assigned to any of the three shutter output pins. The user can also combine the following shutter and vsub pulses with logical XOR operations (symbolized via ^) to generate more complex timings (up to four switch positions per line) for mshut, strobe and vsub: shutdown0^vsub0,shut0^ vsub1, shut0^shut1, and shut0^shut2.

subck: three-level output

The AD9923A supports three levels of output from the subck buffer: vh, vmm, and vll. The vh power supply is shared with the v drive output, but the vmm and vll are dedicated medium and low voltage power supplies for the subck buffer. The subck buffer has two inputs: xsubck and xsubcnt. XSBCNT is created by an internal multiplexer that selects from xv1 to xv13, vsg1 to vsg8, mshut, strobe, vsub, shutdown0 to shutdown3, fg_trig, high and low.

By default, the AD9923A operates in a normal SUBCK configuration, with the SUBCK signal pulsed in each VD field (see Figure 64). Sublight pulses occur one after another per line, and the total number of repetitions in the field determines the exposure time. Using the subckpol and subck1tog registers, the subck pulse polarity and toggle position within the line are programmable. The number of subck pulses for each field is programmed in the subcknum register (Address 0x64).

As shown in Figure 64, the subck pulse always starts on the line after the sg active line (specified in the sgactline register of each field). The subckpol, subck1tog, subck2tog, subcknum, and subcksuppress registers, as described in the Updating New Register Values section, are updated at the beginning of the line after the sensor gate line.

subck: high precision operation

The high-precision stencil uses the same way as the normal stencil, but uses an extra register to control the final subck pulse. In this mode, there is one subck pulse per row, but the last subck in the field has an additional subck pulse whose position is determined by the subck2togx register, as shown in Figure 65. Use this mode for higher exposure time resolution. Setting the subck2togx register to its maximum value (0xffffff) will disable the last subck pulse (default).

Subck: run at low speed

Conventional and high precision shutter operation is used when the exposure time is less than one field length. For exposure times longer than one field interval, use slow shutter operation. The AD9923A uses a separate exposure counter to achieve long exposure times. The number of fields for slow shutter operations is specified in the exposurenum register (address 0x63). As shown in Fig. 66, this shutter mode suppresses the output of subck and vsg over 0 fields to 4095 fields (virtual disk cycles). The VD and HD outputs can be set to 1 by programming the vdhdoff register during exposure.

To generate slow shutter operation, a long exposure is triggered by writing to trigger register bit d3. When this bit is set high, the AD9923A starts the exposure operation on the next VD edge. If a value greater than 0 is specified in the exposurenum register, the AD9923A suppresses the subck output on subsequent fields.

If the exposure is generated using the trigger register, and the exposurenum register is set to 0, the behavior of subck is the same as during normal shutter operation or high precision shutter operation (where the trigger register is not used).

subck: suppress

Typically, subck starts pulsing on the line after the sensor gate line (vsg). Some CCDs need to suppress sub-k pulses for one or more lines following the vsg line. The subcksuppress register enables this suppression.

reading after exposure

After exposure, CCD data is read from sensor gate (vsg) operation. By default, the AD9923A generates VSG pulses in each field. When only one exposure and readout frame is required, as in the CCD preview mode, the vsg and subck pulses can work in each field.

However, typically during readout, the subck output must be suppressed until readout is complete. The readoutnum register specifies the number of additional fields after exposure to continue suppressing subck. readoutnum can be programmed from 0 to 7 fields and should be preprogrammed at startup, not at the same time as the exposure write. A typical interlaced CCD frame readout mode typically requires two sub-light-speed suppressing fields (readoutnum=2) during readout. Three-field six-phase CCDs require three sub-light suppressing fields (readoutnum=3) after readout begins. If the subck output is required to initiate a backup during the last read field, program the readoutnum register to one less than the total number of ccd read fields. Similar to the exposure operation, the readout operation must be triggered using the trigger register.

subck: additional masking

The subckmask register (address 0x65) allows more complex subck masking. If subckmask=1, it will start masking the execution of Subck on the next virtual disk edge. If subckmask=2, it allows the user to select the internal shut3 signal and create custom subck masking patterns across multiple fields.

As previously described in the post-exposure readout section, the AD9923A outputs the subck and vsg signals on each field by default when the trigger register is used to generate the exposure. This works well for continuous single-field exposure and readout operations such as those in CCD live preview mode. However, if CCDs require longer exposure times, or if multiple readout fields are required, trigger registers are required to initiate specific exposure and readout sequences.

Typically, the exposure and readout bits in the trigger register are used together. This will initiate a full exposure plus readout operation. After exposure, reading occurs automatically. The values in the exposure and readoutnum registers determine the length of each operation.

The readout operation can be triggered independently without triggering the exposure operation. This causes the readout to occur at the next vd, and the subck output is suppressed according to the value set in the readoutnum register.

The flip-flop registers also control the shutdown and vsub signals. Each signal is individually controlled but depends on the triggering of exposure and readout operations. Complete example for triggering exposure and readout operations.

Alternatively, exposure and readout operations can be manually controlled by carefully updating the subcksuppress and vsg mask registers on each vd field. Some or all of the manual control of the shutter signal is possible, as described in the following sections. This allows custom exposure/readout/shutter signal timing to be generated.

shutter output

The AD9923A contains three shutter output pins: vsub, mshut, and strobe. Internally, six possible shutter signals are available: vsub0, vsub1, shut0, shut1, shut2, and shut3. Any of these signals, and the following combinations: shut0 ^vsub0, shut0 ^vsub1, shut0 ^shut1, shut0 ^shut2, can be mapped to any output pin using the vsub_ctrl, mshut_ctrl, and strobe_ctrl registers. The vsub signal behaves differently than the off signal and is typically used for vsub output pins. If you need a more general approach to the shutter signal, you can use the shutdown signal for the vsub output pins. It is also possible to configure the sync pins as outputs and use the testo_ctrl register function to send one of the internal shutter signals or a combination listed above to the sync pins. This provides the flexibility to output up to four shutter outputs without the need for an external sync input function.

vsub signal operation

The CCD readout bias (vsub) can be programmed to accommodate different CCDs. Figure 67 shows the two available modes. In mode 0, the vsub becomes active when exposure begins in the field of the last subframe. The open position (rising edge in Figure 67) can be programmed to any line in the field. The vsub is active until the end of the image readout. In mode 1, the vsub is not activated until readout starts. There is also a function called vsub_keepon. When the appropriate vsub_keepon bit is set high, the vsub output remains active even after the readout is complete. To disable vsub later, return this bit low.

The AD9923A contains two programmable VSUB signals: VSUB0 and VSUB1. These signals can be mapped to vsub output pins, mshut pins, or strobe pins.

Close signal operation

Close signal operation: There are three different ways to use the close signal: automatic trigger, single trigger and manual control.

automatic trigger

Typically, the shutdown signal is triggered using the trigger register in conjunction with exposure or readout operations. Using the field, the off and off positions are fully programmable to anywhere within the exposure period (off/off), line (off/off) and pixel (off/off) registers.

The field register defines fields that use row and pixel values based on the value of the exposure counter. The open and closed positions can occur when the field contains the last subck (exposure field 0), or at the latest in the last exposure field before readout begins. Separate field registers allow open and closed positions to appear in different exposure fields.

one-shot

The shutdown signal can be triggered without triggering an exposure or readout operation. In this case, the off signal is triggered using the trigger register, but the exposure bit is not triggered. Both closed and open positions appear in the next field, and the close/close register value is ignored. One-shot operation is useful if a pulse is required immediately in the next field without exposure or readout. In addition, one-shot operation is useful when exposure or readout operations are manually generated without the use of trigger registers, and when subck and vsg masking is manually controlled.

Note that a single-shot action cannot be performed if an exposure action has already been triggered. Automatically turn off signals; trigger mode if they and exposure operations have been triggered.

Manual control

Any shutdown signal can be controlled in manual control mode instead of using the trigger register to activate it. In this mode, individual on and off lines and pixel positions are used individually according to the state of the manual signal control register. Note that only one switch position can be used in a VD interval, either closed or open. As with one-shot operation, the shutdown_on_fd/shut_off_fd register values are ignored when manual control is enabled.

Since there is a separate bit to enable manual control of the shutdown signal, this action can be used regardless of the state that triggered the exposure action.

Note: (1) Manual control can be used together with automatic or single trigger operation. If you turn on the close signal with manual control, and then disable manual control, the close signal remains on. If a subsequent trigger action occurs, the On Position toggle is ignored because the signal is already on. In this case, only the closed position can be triggered. (2) The trigger mechanism of the shutdown signal on AD9923A is different from that of AD9923. On the AD9923, the trigger signal is updated on the update line (register 0x18) of the field written to the trigger register (register 0x61). If the toggle bit of the close signal is deactivated in a given field, this will cause any toggle position of the close signal that occurs after the row to be updated to be ignored. In the AD9923A, the internal trigger signal remains active for the entire row after the trigger register is written. In this case, any toggle positions programmed after updating the row are handled.

trigger action

The AD9923A includes an additional signal that can be used with shutter operation or general system operation. The fg_trigger signal is an internally generated pulse that can be output on a sync pin for shutter or other system functions. A unique feature of the fg_trig signal is that it is output relative to the mode register field state.

The fg_trig signal is generated using the shut1 start polarity and switch position registers, programmable for line and pixel resolution. The field register for SHUT1 is ignored because the field position of the fg_trigger pulse matches the field count specified by the mode register operation. The fg_trigen register contains a three-bit value specifying which field count contains the fg_trigen pulse. Figure 72 shows how these registers are used to generate the fg_trigger pulse. After specifying the fg_trig signal, it can be enabled using bit 3 of the fg_trigen register. If the sync pin is configured as an output (syncenable=0), the fg_trig signal is mapped to the sync output.

Mock Frontend Description/Operation

The AD9923A signal processing chain is shown in Figure 73. Each step is the key to obtaining high-quality images from raw CCD pixel data.

DC recovery

In order to reduce the large DC offset of the CCD output signal, a DC recovery circuit with an external 0.1μf series coupling capacitor is used. This will bring the DC level of the ccd signal back to about 1.5v. A signal with an ADC full-scale range of 2V. Compared to a 1V full-scale system, the equivalent gain range is 0dB to 36dB.

The vga gain curve follows a linear in-db characteristic. The exact VGA gain for any gain register value can be calculated using the following formula

Gain (dB) = (0.0358 × encoding) + 5.5 dB, where the encoding range is 0 to 1023.

Correlated Double Sampler

The cds circuit samples each CCD pixel twice to extract video information and suppress low-frequency noise. The timing shown in Figure 20 illustrates how the reference and data levels of the ccd signal are sampled using two internally generated cds clocks, shp and shd, respectively. The location of the SHP and SHD sample edges is determined by the settings of the SHPLOC and SHDLOC registers at Address 0x37. The placement of these clock signals is the key to getting the best CCD performance.

cds gain can be set to −3db, 0db (default), +3db or +6db

In the cdsgain register, address 0x04. The +3dB and +6dB settings improve noise performance but reduce input range.

Variable Gain Amplifier

The VGA stage offers 6dB to 42dB of gain and is programmable with 10-bit resolution via the serial digital interface. A minimum gain of 6dB is required to match a 1V input.

analog to digital converter

The AD9923A uses a high-performance ADC architecture optimized for high speed and low power consumption. Differential nonlinear (dnl) performance is typically better than 1lsb. The ADC uses a 2 V input range. Typical linearity and noise performance curves are shown in Figure 6 and Figure 8.

Optical black clip

An optical black clamp loop removes residual offset in the signal chain and tracks low frequency changes in CCD black level. During optical black (masked) pixel intervals on each line, the ADC output is compared to a fixed black level reference selected by the user in the clamplevel register. This value can be programmed between 0 lsb and 255 lsb in 1023 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input via the DAC. Typically, the optical black clip loop is opened once per horizontal line, but this loop can be updated more slowly to suit specific applications. If an external digital clamp is used during postprocessing, the AD9923A optical black clamp can be disabled using a programmable register (Address 0x00, Bit D2). Even when the loop is disabled, the clamp register can still be used to provide programmable offset adjustment. The clpob pulse should be placed during the CCD optical black pixel. It is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulse widths can be used, but clamping noise may increase, reducing the ability to track low frequency changes in the black level. See the Horizontal Clamping and Blanking section for timing examples.

digital data output

The digital output data is latched using the bi-phase register value, as shown in Figure 73. The output data timing is shown in Figure 21 and Figure 22. It is also possible to make the output latch transparent so that the data output from the ADC is valid immediately. Program the doutlatch register, bits d1 to 1, set the output latch to transparent. Data output (three states) can also be disabled by setting Bit d0 of Dual Disable Register 0x01 to 1.

The dclk output can be used for external latching of the data output. By default, the dclk output tracks the value of the biphase register. By changing the dclkmode register, the dclk output can be held in fixed phase, while the biphase register value is ignored.

To optimize the delay between the rising edge of dclk and the transition of the data output, a double delay register is used. By default, the transition from the rising edge of dclk to the data output has a delay of about 8ns. See the High Speed Timing Generation section for more information.

Switching the data output can couple noise into the analog signal path. To minimize switching noise, set the biphase register to the same edge as the SHP sampling location, or up to 11 edges after the SHP sampling location. Other settings can produce good results, but require experimentation. It is recommended not to have a biphasic position between the SHD sampling position and the 11 edges following the SHD position. For example, if shdloc=0, set doutphase to an edge position of 12 or greater. If adjustable phase is not required for the data output, Register 0x01, Bit d1 can be used to keep the output latch transparent.

Data output encoding is usually straight binary, but can be changed to grayscale by setting grayscale register 0x01, bit d2 to 1.

Recommended Power-Up Sequence for Master Mode

When the AD9923A is powered up, the following sequence is recommended (see Figure 75):

1. Turn on the +3 V power supply of the AD9923A and start the master clock (CLI).

2. Turn on the V drive power (VH and VL). There is no limit to the order in which vh and vl can be opened.

3. Reset the internal AD9923A registers by writing 1 to the sw-rst register (Address 0x10).

4. Load the required registers to configure the required vpat group, v-sequence, field timing information, high speed timing, horizontal timing and shutter timing information.

5. To put the part into normal power operation, write 0x04 to the AFE alternate register (bits[1:0], address 0x00) and 0x60 to the TEST3 register 0xEA. If the CLO output is used to drive a crystal, the CLO oscillator can also be powered up by writing a 1 to Register 0x16.

6. By default, the internal timing core remains in the reset state, tgcore_rstb register=0. Write 1 to the tgcore_rstb register (Address 0x15) to initiate internal timing core operations. If the 2× clock is used for the cli input, set the clidivide register (address 0x30) to 1 before resetting the timing core. It is important to wait at least 500µs after starting the main clock (cli) and then reset the timing core, especially if using a crystal or crystal oscillator.

7. Configure the AD9923A for master mode timing by writing a 1 to the master register (Address 0x20).

8. Turn up the VDR_en signal to +3 V to enable the V driver output. If vdr_en=0 V, all V driver outputs=vm, subck=vll.

9. Write 1 to the outcontrol register (Address 0x11). This allows the output to become active after the next synchronous rising edge.

10. Generate synchronization events. If sync is high at power-up, turn the sync input down by at least 100 ns. Then, turn the sync up. This will cause the internal counters to reset and initiate VD/HD operation. The first VD/HD edge allows VD register updates, including VH supply OutControl to enable all outputs. If an external sync pulse is not available, an internal sync pulse is generated by writing to the syncpol register, as described in the Generating a Software Sync Without External Sync Signal section.