General Instructions

The AD9923A is a complete 36 MHz front-end solution for digital cameras and other CCD imaging applications. Similar to the AD9923 product, the AD9923A includes an analog front end (AFE), a fully programmable timing generator (TG) and a 15-channel vertical driver (V driver). Precision Timing 8482 ; the core allows adjustment of high-speed clocks at approximately 600 ps resolution when operating at 36 MHz. The on-chip V driver supports up to 15 channels and can be used with a 5-field 10-phase CCD. The analog front end includes black level clamp, CD, VGA and 12-bit ADC. The timing generator and V driver provide all necessary CCD clocks: RG, H clock, vertical clock, sensor gate, substrate clock and substrate bias control. Internal registers are programmed using a 3-wire serial interface. The AD9923A is packaged in an 8 mm × 8 mm CSP_BGA and has an operating temperature range of -25°C to +85°C.

the term

Differential Nonlinearity (DNL)

The ideal adc shows transcoding at exactly 1 lsb intervals. dnl is the deviation from this ideal value. Therefore, each code must have a limited width. Guaranteed no missing codes at 12-bit resolution means that all 4096 codes must be present separately under all operating conditions.

Integral Nonlinearity (inl)

The deviation of each code measured from a true straight line between zero and full-scale values. The point used as the zero scale occurs 0.5 lsb before the first code transition. Positive full scale is defined as the 1.5-level LSB after the last code transition. Measure the deviation from the middle of each output code to a true straight line.

peak nonlinearity

Peak nonlinearity, a complete signal chain specification, refers to the peak deviation of the AD9923A output from a true straight line. The point used as the zero scale occurs 0.5 lsb before the first code transition. Positive full scale is defined as the 1.5-level LSB after the last code transition. Measure the deviation from the middle of each output code to a true straight line. The error is expressed as a percentage of the 2V ADC full-scale signal. The input signal is always appropriately amplified to meet the full-scale range of the ADC.

total output noise

The rms output noise is measured using the histogram technique. The standard deviation of the ADC output code is calculated in LSB and represents the rms noise level of the entire signal chain at a specified gain setting. Using this relationship, the output noise can be converted into an equivalent voltage

1 LSB = (ADC full scale/2N codes), where N is the bit resolution of the ADC, and 1 LSB is 0.488mV.

Power Supply Rejection (PSR)

PSR is measured by a step change applied to the power supply pin. The psr specification is calculated from the change in data output for a given supply voltage step change.

theory of operation

Typical system block diagram of the AD9923A in master mode. The CCD output is processed by the AD9923A AFE circuit, which consists of the CDS, VGA, black level clamp, and ADC. The digitized pixel information is sent to a digital image processor chip for post-processing and compression. To operate the CCD, the CCD timing parameters are programmed into the AD9923A from the system microprocessor through a 3-wire serial interface. The AD9923A generates the CCD horizontal, vertical and internal AFE clocks from the system master clock cli. cli is provided by image processor or external crystal. External synchronization is provided by the microprocessor's sync pulse, which resets the internal counter and resynchronizes the VD and HD outputs. Alternatively, the AD9923A can operate in slave mode, where the vd and hd are supplied from outside the image processor. In this mode, the AD9923A timing is synchronized with VD and HD.

H drivers for HL, H1 to H4, and RG are included in the AD9923A, allowing these clocks to be connected directly to the CCD. Supports H driver voltage HVDD up to 3.3 V. External V drivers are required for vertical transfer clock, sensor gate and substrate clock. The AD9923A also includes a programmable MShut and a strobe output that can be used to trigger the mechanical shutter and strobe (flash) circuits.

Maximum horizontal and vertical counter size for the AD9923A. Internal horizontal and vertical clocks are controlled by these counters to specify line and pixel positions. The maximum hd length is 8192 pixels per line, and the maximum vd length is 4096 lines per field.

Precision Timing

High-Speed Timing Generation The AD9923A uses a flexible precision timing core to generate high-speed timing signals. This core is the basis for generating timing for the CCD and AFE. It consists of reset gate (rg), horizontal drivers (h1 to h4 and hl) and sampling clock (shp and shd). The unique architecture allows system designers to optimize image quality with precise control of horizontal CCD readouts and afe-correlated double sampling. The high-speed timing of the AD9923A operates the same in master and slave modes. For more information on synchronization and pipeline delays, see the Power-Up and Synchronization in Slave Mode section.

Timing resolution

The precision timing core uses the 1x master clock input (cli) as a reference. The frequency of this clock should match the ccd pixel clock frequency. Figure 17 illustrates how the internal timing core divides the master clock cycle into 48 steps or edge locations. Using the 36mhz cli frequency, the edge resolution of the precision timing core is about 0.6ns. If the 1× system clock is not available, the 2× reference clock can be used by programming the clidivide register (Address 0x30). The AD9923A then internally divides the cli frequency by 2. The AD9923A includes a master clock input (CLO), which is the opposite of the CLI. This output is used as a crystal driver. A Crystal can be placed between the cli and clo pins to generate the master clock for the AD9923A.

High-speed clock programmability

Figure 18 shows how the rg, hl, h1 to h4, shp and shd high speed clocks are generated. The rg pulse has programmable rising and falling edges and can be inverted using polarity control. The HL, H1 and H3 horizontal clocks have programmable rising and falling edges and polarity control. The h2 and h4 clocks are opposite to the h1 and h3 clocks, respectively. Table 10 summarizes the high-speed timing registers and their parameters. Figure 19 shows a typical 2-phase H clock operation, where H3 and H4 are programmed to the same edge locations as H1 and H2. The edge position register is 6 bits wide, but only 48 valid edge positions are available. Therefore, the register values are mapped into four quadrants, each containing 12 edge locations. Table 11 shows the correct register values for the corresponding edge locations. Figure 20 shows the default timing positions for the high-speed clock signal.

H driver and RG output

In addition to programmable timing positions, the AD9923A has on-chip output drivers for the RG and H1 to H4 outputs. These drives are powerful enough to drive ccd inputs directly. By using the H1 to H4, HL, and RGDRV registers (Address 0x36), the H driver and RG current can be adjusted for optimal rise/fall times under a specific load. The 3-bit driver settings for each output are adjustable in 4.1 mA increments, with a minimum setting of 0 equal to 0 mA or three states, and a maximum setting of 7 equal to 30.1 mA. As shown in Figure 18, Figure 19 and Figure 20, the H2 and H4 outputs are opposite to the H1 and H3 outputs, respectively. The h1/h2 crossover voltage is about 50% of the output swing. Crossover voltage is not programmable.

digital data output

The AD9923A data output and DCLK phase can be programmed using the bi-phase register (Address 0x38, Bits[5:0]). Any edge from 0 to 47 can be programmed as shown in Figure 21. Normally, the dout and dclk signals track in phase according to the contents of the biphase register. The dclk output phase can also be held fixed relative to the data output by setting the dclkmode register high (Address 0x38, Bit[8]). In this mode, the dclk output remains in a fixed phase equal to the delayed cli version, and the data output phase remains programmable. See the Analog Frontend Instructions/Operations section for more details.

There is a fixed output delay from the rising edge of dclk to the transition of dout, called t. Using the dout delay register (Address 0x38, Bits[10:9]), this delay can be programmed to four values between 0 ns and 12 ns. The default value is 8 ns. The OD of the pipe delay through the AD9923A is shown in Figure 22. After sampling the CCD input via the shd, there is a 16-cycle delay before data is available.

1. The displayed timing value is shdloc=0, dclkmode=0.

2. The value of the right shd and/or doutphase shift dout transition is higher relative to the cli position.

3. The suppression time of the dout phase is defined by tdoutinh, which is equal to shdloc plus 11 edges. The 12 edge locations after shdloc are not recommended for biphasic locations.

4. The recommended value of doout phase is to use shploc edge or 11 edges after shploc.

5. The recommended value of TOD (double) is 4ns.

6. The dual latch can be bypassed using Register 0x01, Bit[1]=1, so that the ADC data output appears directly on the data output pin. This configuration is recommended if adjustable biphase is not required.

Horizontal clamping and blanking

The AD9923A horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Periods provide separate controls for CLPOB, PBLK, and HBLK for different areas of each domain. This allows changing dark pixel clamping and blanking patterns at each stage of readout to accommodate different image transfer timings and high-speed line movements.

Single CLPOB and PBLK mode

The AFE level timing consists of CLPOB and PBLK as shown in Figure 23. These two signals are independently programmed using the registers in Table 12. spol is the start polarity of the signal, and tog1 and tog2 are the first and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly. Individual modes of clpob and pblk can be programmed for each v-sequence. As described in the vertical timing generation section, multiple v-sequences can be created, each containing a unique pulse pattern for clpob and pblk.

Figure 46 shows how a sequence change position divides the readout field into regions. Each region can be assigned a different v-sequence such that the clpob and pblk signals change with each change in vertical timing. Unused CLPOB and PBLK toggle positions should be set to 8191.

CLPOB and PBLK masked regions

The AD9923A allows the CLPOB and/or PBLK signals to be disabled on certain lines in the field without changing the existing CLPOB and/or PBLK mode settings. To use CLPOB masking, program the CLPMaskStart and CLPMaskend registers to specify the start line and end line in fields that ignore CLPOB mode. There are three sets of CLPMaskStart and CLPMaskend registers that allow the creation of up to three CLPOB masked regions. CLPOB mask registers are not specific to a given V sequence; they are active for any existing timing fields. To disable the clpob masking feature, set these registers to a maximum value of 0xfff (default). To use pblk masking, the pblkmaskstart and PBLkmaskend registers are programmed to specify the start and end lines in fields that ignore PBLK patterns. There are three sets of pblkmaskstart and pblkmaskend registers that allow up to three pblk mask regions to be created.

The pblk mask registers are not specific to a given v-sequence; they are active for any existing timing fields. To disable the pblk masking feature, set these registers to a maximum value of 0xfff (default).

Single HBLK mode

The programmable timing of hblk shown in Figure 26 is similar to clpob and pblk; however, no polarity control is enabled. Only the toggle position is used to specify the start and end position of the blanking period. In addition, there is a polarity control register hblkmask that specifies the polarity of the horizontal clock signal during blanking. Set hblkmask high to set h1=h3=high, h2=h4=low, as shown in Figure 27. Like the clpob and pblk registers, the hblk register is available in every v-sequence, allowing different blanking signals to be used with different vertical timings. Note that 8189 is the recommended setting for any unused HBLK toggle positions on the AD9923A. The setting of HBLK mode register HBLKALT. 8190 and 8191 are invalid settings for hblk toggle positions that are not used and cause unwanted hblk toggle activity.

Generate special hblk patterns

HBLK has six toggle positions. Typically, only two toggle positions are used to generate standard hblk intervals. However, additional toggle positions can be used to generate special HBLK patterns, as shown in Figure 28. The pattern in this example uses all six switching positions to generate two additional sets of pulses during the hblk interval. By changing the toggle position, different modes can be created.

Generate hblk line alternation

The AD9923A can alternate between different HBLK toggle positions on the parity line. This function can be used in combination with V-parity alternation or alone. When 1 is written to the hblkalt register, hblktoge1 and hblktoge2 are used for odd lines, and hblktoge3 to hblktoge6 are used for even lines. Writing 2 to the hblkalt register gives the opposite result hblktoge1 and hblktoge2 are used for even rows, and hblktoge3 to hblktoge6 are used for odd rows. When 3 is written to the hblkalt register, all six even toggle positions hblktoge1 through hblktoge6 are used on even lines. There are six additional toggle positions, hblktogo1 to hblktoge6, for odd rows. These registers are normally used for vpat group a, vpat group b, and freeze/resume functions, but when hblkalt=3, these registers become the odd row toggle positions for hblk. By writing 4, 5, 6 or 7 to HBLKALT. In these modes, different registers hblkstart, hblkend, hblklen and hblkrep and four toggle positions are used to generate the hblk mode. This allows for multiple repetitions of the HBLK signal, as shown in Figure 32.

Increasing the h clock width during hblk The AD9923A allows the H1 to H4 pulse width to be increased during the HBLK interval. The H clock pulse width can be increased by reducing the H clock frequency. The hblkwidth register (Register 0x35, Bits[6:4]) is a 3-bit register that allows the h clock frequency to be reduced by 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, or 1/ 14. Frequency reduction occurs only for h1 to h4 pulses located within the hblk region.

Horizontal Timing Example

Figure 33 shows an example of a CCD layout. The horizontal register contains 28 dummy pixels that appear on each line clocked from the ccd. In the vertical direction, there are 10 black (ob) lines at the front end of the readout and 2 black (ob) lines at the back end of the readout. The horizontal direction has four ob pixels in the front and 48 ob pixels in the back.

Figure 34 shows the basic sequence layout used during active pixel readout. The 48 ob pixels at the end of each row are used for the clpob signal. PBLK is optional and is typically used to blank the digital output during invalid CCD pixels. hblk is used during vertical shift intervals.

The HBLK, CLPOB, and PBLK parameters are programmed in the V-Sequence register. Finer clamping solutions. The HBLK width register is used, for example, to add a separate sequence for clamping during an entire row of ob pixels. This requires configuring a separate v-sequence to read the ob line. The clpmaskstart and clpmaskend registers can be used to disable clpob on several lines without affecting the setting of the clamp sequence.

vertical timing generation

The AD9923A provides a very flexible solution for generating vertical CCD timing; it can support multiple CCDs and different system architectures. The 13-phase vertical transfer clocks, xv1 to xv13, are used to move the pixel lines into the ccd's horizontal output registers. The AD9923A allows these outputs to be individually programmed into various readout configurations using the four-step process shown in Figure 35.

1. Use the vertical pattern bank registers to create separate pulse patterns for xv1 to xv13.

2. Use v-pattern groups to build sequences and add more information.

3. Construct the readout of the entire field by dividing the field into regions and assigning each region a sequence. Each field can contain up to nine regions to accommodate different steps of readout, such as high-speed line shifting and unique vertical line shifting. The total number of v-modes, v-sequences and fields is programmable and limited by the number of registers. High-speed line displacement and unique vertical transport are examples of different steps required for readout.

4. Use the mode register to combine fields in any order for various readout configurations.

Vertical Mode (VPAT) Group

The vertical pattern (vpat) group defines an individual pulse pattern for each xv1 to xv13 output signal. Table 15 summarizes the registers available to generate each vpat group. The first, second, third, fourth, fifth and sixth toggle positions (xvtog1, xvtog2, xvtog3, xvtog4, xvtog5, xvtog6) are the pixel positions of the pulse transitions. All toggle positions are 13-bit values that can be placed anywhere on the horizontal line. More registers are included in the vertical sequence register to specify the output pulses: xv1pol to xv13pol specify Table 15. Vertical pattern group register, for each signal's starting polarity, vstart specifies the starting position of the vpat group, and vlen specifies the total length of the vpat group, which determines the number of pixels between each pattern repetition if repetitions are used. For best noise performance make sure vstart+vlen

Vertical Sequence (VSEQ)

Vertical sequences (vseq) are created by selecting one of the v-pattern groups and adding repetition, starting position and horizontal clamping and blanking information. Program each VSEQ using the registers shown in Table 16. Figure 37 shows how each register is used to generate the v-sequence.

The vpatsela and vpatselb registers select the v-mode group used in a given v-sequence. There are two available groups allowing each vertical output to be mapped to a different v-mode group. The selected v-mode group can add repeats for high-speed line shifting or line packing by using the vrep register for parity lines. Usually, the number of repetitions in both registers is the same. If a different number of repetitions is required on odd and even lines, separate values can be used for each register (see Line alternation for generating v-sequences and hblk segments). The vstarta and vstartb registers specify the pixel location at which the v-mode group begins. The vmask register is used in conjunction with the freeze/resume register to enable optional masking of the xv output. One or both of these can enable the Freeze1/Resume1 and Freeze2/Resume2 registers.

The line length (in pixels) is programmable using the hdlen register. Each v-sequence can have different line lengths to accommodate various image readout techniques. The maximum number of pixels per line is 8192. Note that the last row of a field can be individually programmed using the hdlast register located in the field register.

Group A/Group B selection

The AD9923A has the flexibility to use two V-groups in a vertical sequence. In general, all vertical outputs use the same v-mode group in a sequence, but some outputs can be assigned to different v-mode groups. This is useful in some CCD readout modes. The groupsel register is used to select group a or group b for each xv output (lsb is xv1, msb is xv13). Setting each bit to 0 will select group A; setting each bit to 1 will select group B. If only one V-group is required for the vertical output, Group A is used by default (GroupSel=0), and the output uses the V-group specified by the VPATSela register.

If Bank B flexibility is required, use the vpatselb register in the bank select register. For example, Figure 38 shows the output of xv12 and xv13 using a separate v-group b to perform special ccd timing.

Another application of Bank A and Bank B registers is to combine two VPAT banks for more complex patterns. This is achieved by setting both bank registers to 1. Figure 39 shows an example of such timing. When both_groups = 1, both group A and group B toggle positions are used. Also, when both groups = 1, the length, start polarity and number of repetitions are all determined by the appropriate registers for group A. Figure 40 shows a more complex operation combining groups A and B with repetitions.

The v-sequence alternates with the generation line of hblk

During low resolution readout, some CCDs require different numbers of vertical clocks on alternate lines. The AD9923A can support this CCD by using different VREP registers. This allows different numbers of vpat repetitions to be programmed on odd and even rows.

Note that only the number of repetitions in the parity row differs, but the vpat group remains the same. There are separate controls for designated Group A and Group B modes. Both groups A and B support alternate parity lines. Group A uses VREPA_1 and VREPA_2 registers; Group B uses VREPB_odd and VREPB_even registers. Group A can also support three- and four-wire alternation using the VREPA_3 and VREPA_4 registers.

Additionally, the hblk signal can be used alternately for parity lines. When hblkalt=1, the hblktoge1 and hblktoge2 positions are used on odd-numbered lines, and the HBLKToge3 to HBLKToge6 positions are used on even-numbered lines. This allows the hblk spacing to be adjusted on parity lines if needed.