feature

Logically 4-kbit Ferroelectric Random Access Memory (F-RAM) organized in 512 x 8 High Endurance 10 Trillion ( 1013 ) Read/Write 121 Year Data Retention Period (see Data Retention and Endurance Table)

nodelay 8482 ; written in advanced high reliability ferroelectric process very fast Serial Peripheral Interface (SPI) up to 14 MHz frequency Direct replacement for serial flash and EEPROM Hardware support for SPI mode 0 (0, 0) and mode 3 (1 , 1) Complex write protection scheme Hardware protection using write protect (WP) pin Software protection using write disable instruction Software block protection of 1/4, 1/2 or the entire array Low power consumption 300 μA Active power at 1 MHz Current 10μA (typ) Standby current at +85°C Voltage operation: VDD=4.5 V to 5.5 V Auto-E temperature: –40°C to +125°C 8-pin Small Outline Integrated Circuit (SOIC) package AEC Q100 Class 1 Compliant Restriction of Hazardous Substances (RoHS)

logical block diagram

Function description

The FM25040B is a 4-kbit non-volatile memory using an advanced ferroelectric process. Ferroelectric random access memory or f-ram is non-volatile and performs read and write operations. Similar to a ram. It provides 121 years of reliable data retention while eliminating the complexity, overhead and reliability issues caused by system-level serial flash, eeprom and other non-volatile memory.

Unlike serial flash and eeprom, the fm25040b performs writes at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been successfully transferred to the device. The next train can start without data polling. Also, this product has a sizable write-persistent non-volatile memory compared to other products. The FM25040B is capable of supporting 1013 read/write cycles, or more electrically erasable programmable read-only memory. These features make the fm25040b ideal for non-volatile. In-memory applications that require frequent or fast writes. Examples include data collection, where cycles may be critical where industrial control is required, serial flash or long write times for eeproms can result in data loss. The FM25040B offers a huge benefit to serial users of EEPROM or flash memory as a hardware replacement. This FM25040B adopts high-speed SPI bus, which enhances the high-speed write capability of f-ram technology. Device specifications warrant a temperature range of -40°C to +125°C over the automotive-E temperature range. Data transmission (si/so) The spi data bus consists of two serial data lines si and so to communicate. si is also called master out slave in (mosi) so it is called master slave out (miso). The master issues instructions to the slave through the si pin, and

The slave responds through the SO pin. Multiple slave devices can share the si and so lines described earlier. The fm25040b has two separate si and so pins that allow the use of general purpose ports for microcontrollers that do not have a dedicated SPI bus. To reduce resources on the hardware controller, you can connect the two data tie pins (si, so) together, and tie the fixed and wp pins together.

In this configuration, it only uses three pins. Most Significant Bit (msb) The spi protocol requires that the first bit transmitted is the most significant bit (msb). This pairs address and data transfers. 4-kbit serial f-ram requires an opcode, including address bits, and a word address for any read or write operation. The word address consists of the lower 8-bit address. This 9-bit full address uniquely specifies each byte address.

After the serial opcode selects the slave, CS goes low and the first byte received is considered the opcode for the intended operation. The fm25040b uses standard opcodes for memory access. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of CS and the SO pin remains tri-stated.

status register

The FM25040B has an 8-bit status register. The bit register in Status is used to configure the device.

System configuration without SPI port

SPI mode

The FM25040B can be driven by a microcontroller with SPI. Peripherals operate in one of two modes: spi mode 0 (cpol=0, cpha=0) spi mode 3 (cpol=1, cpha=1) for both modes , the input data is latched on rising SCK edge active from the first rising edge after CS runs. If the clock starts from a high state (mode 3), the first

Consider the rising edge after the clock switch. Output data is available on the falling edge of SCK. Two SPI modes. Clock state in absence of bus master

Transmission data is mode 0 SCK remains at 0 Mode 3 SCK remains at 1 The device detects SPI mode from the state of the SCK pin when the device is selected by lowering the CS pin. If the SCK pin is low when the device is selected, SPI mode 0 is assumed to be high, and the SCK pin is assumed to be high, operating in SPI mode 3.

wren - set write enable latch

The FM25040B will power up with writes disabled. Wren commands must be issued before any write operations. Sending the wren opcode allows the user to issue subsequent opcodes for write operations. These include writing to the status register (wrsr) and writing to memory (write). Sending the wren opcode causes an internal write enable to set the latch. A flag bit in the status register, called WEL, indicates the state of the latch. wel='1' means writing is allowed. Attempting to write a WEL bit in the status register has no effect on the state of that bit - only the wren opcode does

Set this bit. The WEL bit will automatically clear the cs edge after a wrdi, wrsr or write operation when rising. This prevents further writes to the Status Register or F-RAM array without another wren command. Figure illustrates the wren command bus configuration. Note: The FM25040B section does not clear memory locations from 0x100 to 0x1FF (write) operations after the Write Enable Latch (WEL) bit in the Status Register performs a memory write.

Wren bus configuration

Without a fix plan, all FM25040B parts in production will continue to perform the above errata.