General Instructions
The w25q64cv (64m-bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. The flexibility and performance of the 25Q series far exceeds that of ordinary serial flash devices. They are great for code tracing to RAM, executing code directly from dual/quad spi (xip), and storing speech, text and data. The device operates on a 2.7V to 3.6V supply with current consumption as low as 4mA active and 1 microA off.
The w25q64cv array is organized into 32768 programmable pages of 256 bytes each. A maximum of 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), 128 groups (32KB block erase), 256 groups (64KB block erase) or the entire chip (chip erase). w25q64cv has 2048 erasable sectors and 128 erasable blocks respectively. Small 4KB sectors allow for greater flexibility in applications requiring data and parameter storage.
W25Q64 cv supports standard serial peripheral interface (SPI), high performance dual/quad output and dual/quad I/O SPI: serial clock, chip select, serial data I/O0 (DI), I/O1 (DO) , I/O2 (/WP) and I/O3 (/HOLD). Supports SPI clock frequencies up to 80MHz, allowing dual I/O equivalent clock frequencies of 160MHz (80MHz x 2) and quad I/O equivalent clock frequencies when using fast-read dual/quad I/O instructions is 320MHz (80MHz x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash. Continuous read mode allows efficient memory access, and the instruction overhead of reading a 24-bit address is only 8 clocks, allowing true xip (execute-in-place) operations.
A hold pin, write protect pin and programmable write protect, top or bottom array control, provide further control flexibility. Additionally, the device supports jedec standard manufacturer and device identification with a 64-bit unique serial number.
2. feature
Spiflash Memory Family – W25Q64cv: 64Mbits/8Mbytes (8388608)
– 256 bytes per programmable page – Standard spi: clk, /cs, di, do, /wp, /hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /HOLD
– Four SPIs: CLK, /CS, IO0, IO1, IO2, IO3
Highest Performance Serial Flash – 80MHz Dual/Quad SPI Clock – 160/320MHz Equivalent Dual/Quad SPI
– 40MB/s sequential data transfer rate – Up to 8 times faster than normal serial flash – Over 100,000 erase/program cycles (1)
– Over 20 years of data retention Efficient "Continuous Read Mode"
– Low instruction overhead – Consecutive reads, 8/16/32/64 byte wraps – Only 8 clocks to address memory – Allows true xip (execute in place) operations – Better than x16 parallel flash efficient” "Continuous Read Mode" – Single 2.7 to 3.6V Supply – 4MA Active Current, <1µA Power Down (Typical)
-40°C to +85°C Operating Range Flexible Architecture with 4KB Sectors - Unified Sector/Block Erase (4/32/64K Bytes)
– Program 1 to 256 bytes – Erase/Program Suspend and Resume Advanced Security Features – Software and Hardware Write Protection – Top/Bottom, 4KB Supplemental Array Protection – Power Lock and OTP Protection – 64-bit Unique ID per Device
– Found Parameter (SFDP) Register – 3x256 Byte Security Register with OTP Lock – Volatile and Non-Volatile Status Register Bit Space Saving Pack – 8-pin SOIC 208 mil
– 8 pad wson 6x5 mm/8x6 mm (2)
– 16-pin SOIC 300 mil
– 8-pin PDIP 300 mil
– 24 Ball TFBGA 8x6mm – Contact Winbond for KGD and other options Note 1. Over 100,000 block erase/program cycles for industrial and automotive temperatures; over 10,000 full chip erase/program cycles per AEC-Q100 test.
2. wson 8x6 mm is a special ordering package, please contact winbond for ordering information.
three. Package Type and Pin Configuration
The W25Q64Cv is available in 8-pin SOIC 208 mil (package code SS), 8-pin WSON 6x5 mm or 8x6 mm (package code ZP&ZE), 8-pin PDIP 300 mil (package code DA), 16-pin SOIC 300 mil (package code SF) and A 24-ball 8x6 mm TFBGA (package code TC) is available as shown in Figure 1A-E. Packaging drawings and dimensions are at the end of this data sheet.

W25Q64Cv pinout, 8-pin SOIC 208 mil (package code SS)

3.2 pad configuration wson 6x5 mm/8x6 mm

W25Q64Cv pad assignment, 8 pad wson 6x5 mm/8x6 mm (packaging code ZP&ZE)

W25Q64Cv pinout, 8-pin PDIP 300 mil (package code DA)

W25Q64Cv pinout, 16-pin SOIC 300 mil (package code SF)

Pin Description
4.1 Chip Select (/cs)
The spi chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (do or io0, io1, io2, io3) pins are at high impedance. When deselected, device power consumption is in standby unless an internal erase, program, or write status register cycle is in progress. When /cs is lowered, the device will be selected, power consumption will increase to the active level, and commands can be written to and data read from the device. After power up, /cs must transition from high to low in order to accept new commands. The /CS input must track the VCC supply level at power-up (see "Write Protection" and Figure 38). This can be done using the pull resistor on /cs if desired.
4.2 Serial data input, output and IOS (DI, DO and IO0, IO1, IO2, IO3)
W25Q64cv supports standard SPI, dual SPI and quad SPI operation. Standard SPI instructions use a unidirectional DI (input) pin to serially write an instruction, address, or data to the device on the rising edge of the serial clock (CLK) input pin. Standard SPIs also use a unidirectional do (output) to read data or status from the device on the falling edge of clk.
Dual SPI and Quad SPI instructions use bidirectional IO pins to serially write commands, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set. When qe=1, the /wp pin becomes io2, and the /hold pin becomes io3.
4.3 Write protection (/wp)
The write protect (/wp) pin can be used to prevent writing to the status register. Used in conjunction with the block protection (cmp, sec, tb, bp2, bp1, and bp0) bits of the status register and the status register protection (srp) bit, sectors as small as 4kb or part of an entire memory array can be hardware protected. The /WP pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /wp pin function is not available because this pin is used for io 2. The pin configuration for quad I/O operation is shown in Figure 1A-E.
4.4 Hold (/hold)
The /hold pin allows to hold the device while it is active. When /hold goes low, when /cs goes low, the do pin will be in high impedance and the signals on the di and clk pins will be ignored (don't care). When /HOLD is high, device operation can resume. The /hold function is useful when multiple devices share the same spi signal. The /HOLD pin is active low. When the qe bit of the status register-2 is set to quad input/output, the /hold pin function is not available since this pin is used for io3. The pin configuration for quad I/O operation is shown in Figure 1A-E.

Serial Clock (CLK)
The SPI serial clock input (CLK) pin provides the timing of serial input and output operations. ("See SPI Operation")
5. block diagram

6. Function description
6.1 SPI Operation
6.1.1 Standard SPI Description
The w25q64cv is accessed through an SPI-compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data in (di), and serial data out (do). The standard SPI instruction uses the DI input pin to serially write an instruction, address, or data to the device on the rising edge of clk. The do output pin is used to read data or status from the device on the falling edge of clk.
SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. The main difference between Mode 0 and Mode 3 is the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the serial flash. For mode 0, the clk signal is typically low on the falling and rising edges of /cs. For Mode 3, the CLK signal is normally high on the falling and rising edges of /cs.
6.1.2 Dual SPI Instructions W25Q64cv supports dual SPI operation when using the "Fast Read Dual Output (3BH)" and "Fast Read Dual I/O (BBH)" instructions. These instructions allow data to be transferred to and from the device at 2 to 3 times the rate of normal serial flash devices. Dual SPI read instructions are great for quickly downloading code to RAM (code shadowing) at power up or executing non-speed critical code directly from the SPI bus (XIP). When using the dual SPI instruction, the di and do pins become bidirectional I/O pins: io0 and io1.
6.1.3 Quad SPI instructions when using "Fast Read Quad Output (6BH)", "Fast Read Quad I/O (EBH)", "Word Read Quad I/O (E7H)" and "Octal W25Q64cv supports quad SPI operation when "word read quad I/O (E3H)" command. These instructions allow data to be transferred to and from the device at 4 to 6 times the rate of normal serial flash. Quad-read instructions provide significant improvements in sequential and random access transfer rates, allowing fast code tracing directly to RAM or execution from the SPI bus (XIP). When using the quad spi instruction, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3, respectively. The quad spi instruction requires the nonvolatile quad enable bit (qe) in Status Register 2 to be set.
6.1.4 Hold function For standard SPI and dual SPI operation, the /hold signal allows w25q64cv operation to be suspended when activated (when /cs is low). The /hold function may be useful in situations where spi data and clock signals are shared with other devices. For example, when priority interrupts need to use the SPI bus, consider whether the page buffer is only partially written. In this case, the /hold function can save the state of the instruction and data in a buffer so that programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and dual SPI operation, not quad SPI operation.
To initiate the A/HOLD condition, a device with /CS low must be selected. If the CLK signal is already low, the A/HOLD state will activate on the falling edge of the /HOLD signal. If CLK is not already low, the /hold condition will activate after the next falling edge of CLK. If the CLK signal is already low, the /HOLD condition will terminate on the rising edge of the /HOLD signal. If CLK is not low, the /hold condition will terminate after the next falling edge of CLK. In the A/HOLD state, the serial data output (do) is high impedance and the serial data input (di) and serial clock (clk) are ignored. The chip select (/cs) signal should remain active (low) for the entire duration of the /hold operation to avoid resetting the device's internal logic state.
6.2 Write Protection Applications using non-volatile memory must consider the possibility of noise and other adverse system conditions that could compromise data integrity. To solve this problem, w25q64cv provides several ways to protect data from accidental writing
6.2.1 Write Protection Features When VCC is below threshold, time delay write disable after device reset power-on Write enable/disable command, automatic write disable after erase or programming Software and hardware using status register (/wp pin) Write-Protect Using Power-Off Command Write-Protect Lockout Write-Protect Until Next Power-Up One-Time Program (OTP) Write-Protect*
NOTE: This feature is available on special order. Please contact Winbond for details.
On power-up or power-down, the W25Q64Cv will remain in reset when VCC is below the threshold of VWI (see power-up timing and voltage levels and Figure 38). When reset, all operations are disabled and no commands are recognized. All program and erase related instructions are further disabled due to the time delay of TPUW during power up and after VCC voltage exceeds VWI. This includes Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instructions. Note that the chip select pin (/cs) must track the VCC supply level at power-up until the VCC minimum level and TVSL delay are reached. This can be done using a pull-up resistor on /cs if desired.
After power-up, the device is automatically in a write-disabled state with the Status Register Write Enable Latch (WEL) set to 0. Before accepting a Page Program, Sector Erase, Block Erase, Chip Erase, or Write Status Register command, the Allow Write command must be issued. The Write Enable Latch (WEL) is automatically cleared to a writable state of 0 upon completion of a program, erase or write instruction.
Software-controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protection (srp0, srp1) and Block Protection (cmp, sec, tb, bp2, bp1, and bp0) bits. These settings allow parts or the entire memory array to be configured as read-only for sectors as small as 4KB. Used in conjunction with the write-protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. See the Status Register section for more information. In addition, the power-down command provides an additional level of write protection because all commands except the release power-down command are ignored.
7. Status Registers and Instructions The Read Status Register-1 and Status Register-2 instructions can be used to provide status of flash array availability, write protection status if the device has write enabled or disabled, quad SPI setup, security register lock status and erase/ Program suspended state. The Write Status Register command can be used to configure the device write protection feature, quad SPI settings and security register OTP lock. Write access to the status register is controlled by the state of the nonvolatile status register protection bits (srp0, srp1), the write enable instruction, and the /WP pin during standard/dual SPI operation.
7.1 Status Register
7.1.1 Busy state (busy)
busy is a read-only bit in the Status Register (s0), when the device executes a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, or Erase/Program Security Register instructions, This bit is set to 1 state. During this time, the device will ignore instructions other than Read Status Register and Erase/Program Suspend instructions (see tw, tpp, tse, tbe, and tce in AC Characteristics). When a program, erase or write status/secure register instruction completes, the busy bit will be cleared to the 0 state, indicating that the device is ready for further instructions.
7.1.2 Write Enable Latch Status (WEL)
The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that is set to 1 after a Write Enable instruction is executed. When the device write is disabled, the WEL status bit is cleared to 0. The write disable state occurs at power-up or after any of the following commands: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register, and Program Security Register.
7.1.3 Block Protection Bits (bp2, bp1, bp0)
The block protection bits (bp2, bp1, bp0) are non-volatile read/write bits in the status registers (s4, s3, and s2) that provide write protection control and status. The block protection bits can be set using the Write Status Register instruction (see tw in AC Characteristics). All, none or part of the memory array can be protected from program and erase instructions (see Status Register Memory Protection Table). The factory default setting of the block protection bit is 0, there is no protected array.
7.1.4 Upper/lower block protection bit (TB)
The non-volatile top/bottom bit (tb) controls whether the block protection bits (bp2, bp1, bp0) are protected from the top (tb=0) or bottom (tb=1) of the array, as shown in the Status Register Memory Protection table . The factory default setting is tb=0. The tb bit can be set with the write status register instruction according to the state of the srp0, srp1 and wel bits.
7.1.5 Sector/Block Protection Bits (Sec)
The non-volatile sector/block protection bits (seconds) control whether the block protection bits (bp2, bp1, bp0) protect 4kb sectors (sec=1) at the top (tb=0) or bottom (tb=1) of the array (sec=1) or 64kb blocks (sec=0) as shown in the Status Register Memory Protection table. The default setting is sec=0.
7.1.6 Complement Protection Bit (CMP)
The complement protection bit (cmp) is a non-volatile read/write bit in the status register (s14). It is used in combination with the sec, tb, bp2, bp1 and bp0 bits to provide greater flexibility for array protection. Once CMP is set to 1, the array protection previously set by SEC, TB, BP2, BP1 and BP0 will be reversed. For example, when cmp=0, the top 4KB sectors can be protected while the rest of the array is not; when cmp=1, the top 4KB sectors become unprotected and the rest of the array becomes Read only. See the Status Register Memory Protection table for details. The default setting is cmp=0.
7.1.7 Status Register Protection Bits (SRP1, SRP0)
Status register protection bits (srp1 and srp0) are non-volatile read/write bits in the status registers (s8 and s7). The srp bit controls the method of write protection: software protection, hardware protection, power lock, or one-time programmable (otp) protection

7.1.8 Erase/Program Suspended Status (SUS)
The Suspend Status bit is a read-only bit in the Status Register (s15) that is set to 1 after an Erase/Program Suspend (75h) instruction is executed. The SUS status bit is cleared to 0 by the Erase/Program Resume (7AH) instruction and power down and power cycle.
7.1.9 Security Register Lock Bits (lb3, lb2, lb1)
The secure register lock bits (lb3, lb2, lb1) are non-volatile one-time program (otp) bits in the status registers (s13, s12, s11) that provide write protection control and status to the secure registers. The default state of lb[3:1] is 0 and the security registers are unlocked. lb[3:1] can be individually set to 1 using the write status register instruction. LB[3:1] are one-time programmable (OTP), once set to 1, the corresponding 256-byte security register will permanently become read-only.
7.1.10 Four Enable Bit (QE)
The quad enable (qe) bit is a non-volatile read/write bit in the status register (S9) that enables quad spi operation. When the qe bit is set to the 0 state (factory default), the /wp pin and /hold are enabled. When the qe bit is set to 1, the four io2 and io3 pins are enabled and the /wp and /hold functions are disabled.
Warning: The QE bit should not be set to 1 if the /wp or /hold pins are connected directly to power or ground during standard spi or dual spi operation.

7.2 Description
The instruction set of w25q64cv consists of 35 basic instructions, which are fully controlled through the spi bus (see instruction set table 1-3). Use the falling edge of chip select (/cs) to start the instruction. The first byte of data coming into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of the clock, most significant bit (msb) first.
Instructions vary in length from one byte to several bytes, possibly followed by address bytes, data bytes, dummy bytes (don't care), and in some cases a combination. The description is done using the rising edge of EDGE/CS. Clock-dependent timing diagrams for each instruction are included in Figures 4 through 37. All read instructions can be completed after any timing bit. However, all write, program, or erase instructions must complete on byte boundaries (/cs driven high after a full 8-bit clock), otherwise the instructions will be ignored. This feature further protects the device from accidental writes. In addition, when memory is being programmed or erased, or when the status register is written, all instructions except read status register are ignored until the program or erase cycle is complete.

7.2.5 Write Allowed (06h)
The write enable instruction (Figure 4) sets the write enable latch (WEL) bit in the status register to 1. The WEL bit must be set before every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Register instructions. Move the instruction code "06h" into the data input (di) pin on the rising edge of clk by driving /cs low, then drive /cs high to enter the write enable instruction.

7.2.6 Volatile Status Register Write Enable (50h)
The non-volatile status register bits described in Section 7.1 can also be written as volatile bits. This allows for greater flexibility in rapidly changing system configurations and memory protection schemes without waiting for typical non-volatile bit write cycles or affecting the persistence of non-volatile bits in the status register. To write a volatile value to a Status Register bit, the Write Enable for Volatile Status Register (50h) instruction must be issued before the Write Status Register (01h) instruction. The write enable (Figure 5) of the volatile status register instruction does not set the write enable latch (WEL) bit, it is only valid for the write status register instruction to change the volatile status register bit value.
Figure 5. Write Enable of Volatile Status Register Instruction Sequence Diagram

7.2.7 Write Prohibited (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to 0. The write disable command is entered by driving /cs low, moving the command code "04h" to the di pin, then driving /cs high. Note that the WEL bit is automatically reset after power-up and after completion of Write Status Register, Erase/Program Security Register, Page Program, Quad Page Program, Sector Erase, Block Erase and Chip Erase commands.
The write disable instruction can also be used to disable the write enable of the volatile status register instruction.

Image 6. Write Disable Instruction Sequence Diagram
7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instruction allows the 8-bit status register to be read. Commands can be entered by driving /cs low and shifting the instruction code "05h" of status register 1 or the instruction code "35h" of status register 2 into the DI pin on the rising edge of CLK. Then, the status register bits are shifted out on the do pin on the falling edge of CLK, the most significant bit (msb) first as shown in Figure 7. The status register bits are shown in Figures 3A and 3B and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE, LB[3:1], CMP and SUS bits (see Status Register earlier in this data sheet part).
The Read Status Register instruction can be used at any time, even if a program, erase or write status register cycle is in progress. This allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The status register can be read continuously, as shown in Figure 7. This command is done by driving /cs high.

7.2.9 Write Status Register (01H)
The Write Status Register instruction allows writing to the Status Register. Only nonvolatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 to 2 of status register 1) and cmp, lb3, lb2, lb1, qe, srp1 (bits 7 to 2 of status register 2) and cmp, lb3, lb2, lb1, qe, srp1 (bits of status register 2) can be written to 14 to 8). All other status register bit positions are read-only and will not be affected by the write status register instruction. LB[3:1] are non-volatile OTP bits, once set to 1, they cannot be cleared to 0. The status register bits are shown in Figure 3 and described in 7.1.
To write to the nonvolatile status register bits, the standard write enable (06h) command must be executed before the device can accept the write status register command (status register bit WEL must be equal to 1). Once the write operation is enabled, enter the command by driving /cs low, send the command code "01h", and then write the status register data byte, as shown in Figure 8.

To write to a volatile status register bit, the write enable of the Volatile Status Register (50h) instruction must be executed before the Write Status Register instruction (status register bit WEL remains 0). However, srp1 and lb3, lb2, lb1 cannot be changed from "1" to "0" due to the OTP protection of these bits. The volatile status register bit values are lost after a power failure, and the nonvolatile status register bit values are restored when power is turned on again.
To complete the write status register command, the /cs pin must be driven at high speed after the eighth or sixteenth data bit of the clock input. If this is not done, the write status register instruction will not be executed. If /cs is driven at high speed after the eighth clock (compatible with 25x series), the cmp and qe bits will be cleared to 0.

During a nonvolatile status register write operation (06h combined with 01h), after /cs is driven high, an auto-timed write status register cycle will begin for a duration of tw (see AC Characteristics). While a write status register cycle is in progress, the read status register instruction can still be accessed to check the status of the busy bit. During the write status register cycle, the busy bit is 1; at the end of the cycle and ready to accept other instructions again, the busy bit is 0. After the write status register cycle is complete, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During a volatile status register write operation (50h combined with 01h), after /cs is driven high, the status register bits will be flushed to the new value for the time period of tshsl2 (see AC characteristics). During the status register bit refresh, the busy bit will remain 0

Read data (03h)

The Read Data instruction allows one or more bytes of data to be read sequentially from memory. The instruction is initiated by driving the /cs pin low, then shifting the instruction code "03h" followed by the 24-bit address (A23-A0) into the DI pin. Code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte at the address memory location will be shifted on the DO pin on the falling edge of CLK, MSB first. After each byte of data has been shifted out allowing a continuous stream of data, the address is automatically incremented to the next higher address. This means that the entire memory can be accessed with a single instruction as long as the clock continues. This command is done by driving /cs high.

The read data command sequence is shown in Figure 9. If a read data command is issued during an erase, program or write cycle (busy=1), the command will be ignored and will not have any effect on the current cycle. The Read Data command allows clock rates from DC to maximum fr (see AC Electrical Characteristics).

7.2.11 Fast Read (0bh)

The fast read command is similar to the read data command, except that it operates at the highest frequency of fr (see AC electrical characteristics). This is achieved by adding 8 "virtual" clocks after the 24-bit address, as shown in Figure 10. A virtual clock allows extra time for the device's internal circuitry to set the initial address. During the dummy clock, the data value on the do pin is "don't care".

7.2.12 Fast Read Dual Output (3BH)

The fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction, except that the data is output on two pins: io0 and io1. This allows transferring data from the w25q64cv at twice the rate of standard spi devices. Fast read dual output instructions are ideal for fast code downloads from flash to RAM at power-up, or for applications that cache code segments to RAM for execution.

Similar to the fast read command, the fast read dual output command can operate at the highest possible frequency of fr (see AC Electrical Characteristics). This is achieved by adding 8 "virtual" clocks after the 24-bit address, as shown in Figure 11. A virtual clock allows the device's internal circuitry to have extra time to set the initial address. Input data during the virtual clock is "don't care". However, before the falling edge of the first data output clock, the IO0 pin should be high impedance.

7.2.13 Fast read quad output (6BH)

The fast read quad output (6BH) instruction is similar to the fast read dual output (3BH) instruction, except that the data is output on four pins, namely IO0, IO1, IO2 and IO3. A quaternary enable of status register 2 must be performed before the device accepts a fast read quaternary output command (status register bit qe must be equal to 1). The fast read quad output instruction allows data transfer from the w25q64cv at four times the rate of standard spi devices.

The fast read quad output command can operate at the highest possible fr frequency (see AC Electrical Characteristics). This is achieved by adding 8 "virtual" clocks after the 24-bit address, as shown in Figure 12. A virtual clock allows the device's internal circuitry to have extra time to set the initial address. Input data during the virtual clock is "don't care". However, before the falling edge of the first data output clock, the IO pins should be high impedance.

7.2.14 Fast Read Dual I/O (BBH)

The Fast Read Dual I/O (BBH) instruction allows improved random access while maintaining two IO pins, IO0 and IO1. It is similar to a fast read dual output (3bh) instruction, but with the ability to input two address bits (a23-0) per clock. This reduced instruction overhead may allow code execution (XIP) directly from dual SPIs in some applications.

Fast read dual I/O with "continuous read mode"

Fast Read Dual I/O instructions can further reduce instruction overhead by setting the "Continuous Read Mode" bit (M7-0) after the input address bit (A23-0), as shown in Figure 13A, (M7-4) The upper nibble controls the length of the next fast read dual I/O instruction by including or excluding the first byte instruction. instruction code. The lower nibble of (m3-0) is unimportant ("x"). However, before the falling edge of the first data output clock, the IO pins should be high impedance.

If "Continuous Read Mode" bit M5-4 = (1,0), the next fast read dual I/O instruction (after /cs is raised and then lowered) does not require a BBH instruction code, as shown in Figure 13b Show. This reduces the instruction sequence by 8 clocks and allows the read address to be entered immediately after /cs is asserted low. If the "Continuous Read Mode" bits m5-4 are not equal to (1,0), the next instruction (raised and then lowered after /cs) requires the instruction code of the first byte, returning to normal operation. The "Continuous Read Mode" reset command can also be used to reset (M7-0) before issuing a normal command (see 7.2.20 for details).

7.2.15 Fast Read Quad I/O (EBH)

The Fast Read Quad I/O (EBH) instruction is similar to the Fast Read Dual I/O (BBH) instruction, except that the address and data bits are input and output through four pins IO0, IO1, IO2, and IO3, and the data output is Four virtual clocks were previously required. Quad I/O greatly reduces instruction overhead, allowing faster code execution random access (xip) directly from the quad SPI. The Quaternary Enable bit (qe) of Status Register 2 must be set to enable Fast Read Quaternary I/O instructions.

Fast read quad I/O with "continuous read mode"

Fast Read Quaternary I/O instructions can further reduce instruction overhead by setting the "Continuous Read Mode" bit (M7-0) after the input address bit (A23-0), as shown in Figure 14A, (M7-4 ) controls the length of the next fast read quad I/O instruction by including or excluding the first byte instruction. instruction code. The lower nibble of (m3-0) is unimportant ("x"). However, before the falling edge of the first data output clock, the IO pins should be high impedance.

If "Continuous Read Mode" bit M5-4 = (1,0), the next fast read quad input/output instruction (after /cs is raised and then lowered) does not require the ebh instruction code, as shown in Figure 14b Show. This reduces the instruction sequence by 8 clocks and allows the read address to be entered immediately after /cs is asserted low. If the "Continuous Read Mode" bits m5-4 are not equal to (1,0), the next instruction (raised and then lowered after /cs) requires the instruction code of the first byte, returning to normal operation. The "Continuous Read Mode" reset command can also be used to reset before issuing a normal command (M7-0)