Architecture Overview
Maxim's ZLF645 family of flash MCUs is a member of the Crimzon infrared family of microcontrollers. This series offers a code upgrade path directly compatible with Crimzon MCUs, provides powerful learning capabilities, and features up to 64 KB of flash memory and 1K of general-purpose random access memory (RAM). Two timers allow complex signals to be generated while performing other counting operations.
A Universal Asynchronous Receiver/Transmitter (UART) allows the ZLF645 MCU to act as a slave/master database chip. The Baud Rate Generator (BRG) can be used as a third timer when the UART is not used. The enhanced stop mode resume function allows the ZLF645 MCU to operate on any logic change and any combination of the 12 SMR inputs. SMR sources can also be used as interrupt sources.
Many high-end remote control units offer a learning function. The learn function allows to replace the remote control unit, from the original remote control unit and regenerate the signal. However, many learning remote control amplifier circuits are expensive and poorly tuned. The ZLF645 MCU is the first to offer a built-in chip-tuned amplifier circuit in a wide range of locations and battery voltages. The only external component required is the photodiode.
The ZLF645 microcontroller greatly reduces the system cost and improves the reliability of the learning function. With all the new features, the ZLF645 microcontroller is ideal for infrared remote control and other microcontroller applications.

Functional Block Diagram Figure 1 shows the functional blocks of the ZLF645 Flash MCU.

Pin Description

Pin configuration package for ZLF645 MCU 20-pin PDIP, SOIC and SSOP.

Pin configuration of ZLF645 MCU in 28-pin PDIP,
SOIC and SSOP packages.

I/O port pin functions
The ZLF645 MCU has up to five 8-bit ports as described below:
1. Port 0 can be programmed as input or output.
2. Port 1 can be byte-programmed as input or output.
3. Port 2 can be programmed as input or output.
4. Port 3 has four inputs in the lower nibble and four outputs in the upper nibble.
5. Port 4 can be programmed as input or output.
Port 0, Port 1, Port 2, and Port 4 disable internal pull-ups on any pin or pin group when programmed to output mode.
The CMOS input buffer for each port 0, port 1, port 2, or port 4 pin is always connected to the pin, even if the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, the high output state may cause the CMOS input buffer to float. This can result in over 100 μA. To prevent this leakage, connect the pin to an external signal level with prescribed logic or ensure its output state is low, especially in stop mode.
Port 0, Port 1, Port 2, and Port 4 all have input and output functions. Input logic is always present whether the port is configured as input or output. when? When executing a read instruction, the MCU reads the actual value of the input logic, but does not read from the output buffer. Additionally, the instructions for or, and, and xor have a readmodify-write sequence. The MCU first reads the port, then modifies the value, then loads back into the port.
If the port is configured as an open-drain output or the port is driving any circuit that makes a voltage different from the corresponding output logic.
If configured as an open-drain output, the output is logic 1 and read back as a zero for the floating port. The following instructions set all p00–p07 low: and p0, %f0 reset (input, low level) reset initializes MCU and completes via power-on reset (POR), watchdog timer (WDT), stop mode resume, Low voltage detection or pass
External reset pin for 48 pin packaged products.

During por and wdt reset, an internally generated reset drives the reset pin low time. Any device driving an external reset line must be open drain to avoid damage from possible conflicting reset conditions. A pull-up is provided internally for the reset pin, if available. When the ZLF645 MCU asserts (low) the reset pin, the internal pull-ups are disabled.
An external reset does not initiate an exit from stop mode.
Registers that control I/O ports. Some port pin functions can also be affected by the control registers of other peripheral functions.

port 0
Port 0 is an 8-bit bidirectional CMOS compatible port. Its eight I/O lines are configured under software control to create a nibble I/O port. The output drivers are push/pull or open drain, controlled by Bit 2 of the port configuration register.
If an I/O operation requires one or two nibbles, it must be done by writing to the port 0/1 mode register. After a hardware reset or stop mode recovery, port 0 is configured as an input port.
When uart tx is enabled, port 0, bit 7 is used as the transmit output of the uart. The I/O function of port 0 bit 7 is overridden by the UART serial output (TXD) when UART is enabled (UCTL[7]=1). The pin must be configured as an output touch pin for TXD data (p01m[6]=0).
An optional pull-up transistor is available as a user-selectable flash programming option on all Port 0 bits, using nibble selection.

Port 1 is an 8-bit bidirectional CMOS compatible I/O port. It can be controlled in software as input or output. Flash programming option bits can be used to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed to push/pull or open the drain. The power-on reset function is configured as an input using eight bits[p17:10] of Port 1.
configuration.

Port 2 is an 8-bit bidirectional CMOS compatible I/O port. Its eight I/O lines can be independently configured as inputs or outputs under software control. Port 2 is always available for I/O operations. A flash programming option bit can be used to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed to push/pull or open the drain. The power-on reset function is configured as an input using Port 2[p27:20].
Port 2 also features an 8-bit input OR and AND gate and edge detection circuitry that can be used to resume from stop mode. Programmable p20 to access edge detection circuitry in demodulation mode. Figure 8 shows the configuration of port 2.

Port 3 is an 8-bit CMOS compatible I/O port. Port 3 consists of four fixed inputs (p33:p30), three fixed outputs (p37:p36:p35), and one multifunction pin (p34), which can be used as output only or as a bidirectional open-drain I/O, It depends on the ZLF645 microcontroller being in inductively coupled plasma mode.
p30, p31, p32 and p33 are standard CMOS inputs with optional pull-up transistors and can be configured as interrupts under software, as receive data input blocks for UART, as inputs to comparator circuits, or as inputs to infrared learning amplifiers .
p37, p36 and p35 are push/pull outputs that can be configured as counter/timer and/or comparator circuits.
During the por time of the zlf645, the p34 is configured as a pull-up enabled input pin. If the zlf645 does not detect this pin low and is put into icp mode after completing the por cycle, the pin will revert to a push/pull output only.