ZL2106
The zl2106 is an innovative power conversion and management chip that integrates an integrated synchronous step-down dc/dc converter with key power management functions in a small package, resulting in a flexible and integrated solution.
The ZL2106 can provide output voltages from 0.54V to 5.5V (with margin) and input voltages from 4.5V to 14V. The internal low rds(on) synchronous power mosfet enables the ZL2106 to efficiently deliver continuous loads up to 6A. Internal Schottky bootstrap diodes reduce discrete component count. The ZL2106 also supports phase expansion to reduce system input capacitance.
Power management functions such as digital soft-start delay and ramp, sequencing, tracking and margin can be configured with simple pin bundles or through the chip serial port. The ZL2106 uses the PMBus protocol to communicate with the host controller and a digital DC bus for interoperability between other Zilker lab equipment.
Features Integrated mosfet switch
6A continuous output current output voltage accuracy is ±1%
Parameter Capture Snapshot
I2C/SMBus interface, PMBus compatible Internal Non-Volatile Memory (NVM)
Telecom, Network, Storage Equipment Test and Measurement Equipment Industrial Control Equipment
5V and 12V Distributed Power Systems

Typical Application Circuit The application circuit below represents a typical implementation of the zl2106. For pmbus operation, it is recommended to connect the enable pin (en) to sgnd.

Ferrite beads can be used to suppress input noise.
The DDC bus pull-up resistors will vary depending on the capacitive loading of the bus, including the number of devices connected. The 10 kΩ default, assuming a maximum of 100 pF per device, provides the necessary 1 microsecond pull-up rise time.
12V to 3.3V/6A Application Circuit (5ms SS Delay, 5ms SS Ramp)
block diagram

ZL2106 Overview of Digital DC Architecture
The ZL2106 is an innovative mixed-signal power conversion and power management integrated circuit based on Zilker Labs patented digital DC technology that provides an integrated high-performance buck converter for point-of-load applications. The zl2106 integrates all necessary pwm control circuits and low rds(on) synchronous power mosfets, providing a very small solution for load currents up to 6A.
Its unique pwm loop uses an ideal combination of analog and digital modules to precisely control the entire power conversion process without software, resulting in a very flexible device that is also very easy to use. An extensive set of power management functions is fully integrated and can be configured using simple pin connections. User configuration can be saved in internal non-volatile memory (nvm). Additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands for maximum flexibility.
Once enabled, the zl2106 is immediately ready to regulate power and perform power management tasks without programming. Advanced configuration options and real-time configuration changes are available via the I2C/SMBus interface if required, and multiple operating parameters can be continuously monitored with minimal interaction from the host controller. The integrated secondary regulation circuit enables single-supply operation on any external supply between 4.5V and 14V, eliminating the need for a secondary bias supply. The ZL2106 can also be configured to operate from a 3.3V or 5V backup supply when the main power rail is not present, allowing the user to configure and/or read diagnostic information from the device when the main power supply is interrupted or disabled.
The ZL2106 can be configured by simply connecting its pins according to the tables provided in the following sections. In addition, a comprehensive set of application notes is provided to help simplify the design process. An evaluation board can also help the user become familiar with the device. This board can be evaluated as a standalone platform using the pin configuration settings. In addition, a Windows 8482 ; based graphical user interface is provided, enabling full configuration and monitoring capabilities via the I2C/SMBus interface using an available computer and included USB cable.
Power Conversion Overview
The zl2106 acts as a voltage mode synchronous buck converter with an optional constant frequency pulse width modulator (pwm) control scheme. The ZL2106 integrates dual low RDS(on) synchronous MOSFETs to minimize circuit footprint.
Basic synchronous buck converter topology for major powertrain components. This type of converter is also called a buck converter because the output voltage must always be lower than the input voltage.

The zl2106 integrates two n-channel power mosfets; qh is the top control mosfet, and ql is the bottom synchronous mosfet

When qh is off (time 1-d), the current through the inductor must continue to flow from ground up through ql, during which time the current gradually decreases. Since the output capacitor cannot exhibit low impedance at the switching frequency, the AC component of the inductor current is filtered out of the output voltage, so the load almost sees the DC voltage.
Typically, buck converters are specified with a maximum duty cycle that effectively limits the maximum output voltage achievable for a given input voltage and switching frequency. This duty cycle limit ensures that during each switching cycle, the low-side MOSFET is allowed to turn on for a minimum time, which allows the bootstrap capacitor to charge and provide sufficient gate drive voltage for the high-side MOSFET.

In general, the size of components l1 and cout and the overall efficiency of the circuit are inversely proportional to the switching frequency fsw. Therefore, the most efficient circuit can be achieved by switching the mosfet at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint can be achieved by switching as fast as possible, but this reduces efficiency. When determining the switching frequency for each application, each user should determine the optimal combination of size and efficiency
In this circuit, the ZL2106 regulates the target output voltage by connecting the vsen pin directly to the output regulation point. The vsen signal is then compared to an internal reference voltage set by the user to the desired output voltage level. The error signal resulting from this comparison is converted to a digital value by an analog-to-digital (A/D) converter. The digital signal is also applied to the adjustable digital compensation filter, and the compensation signal is used to derive the appropriate pwm duty cycle to drive the internal mosfet in a way that produces the desired output.
Power Management Overview
The zl2106 integrates a range of configurable power management functions that are easy to implement without additional components. In addition, the ZL2106 features circuit protection that continuously protects equipment and loads from damage caused by unexpected system failures. The ZL2106 continuously monitors input voltage, output voltage/current and internal temperature. A power-good output signal is also included to enable the power-on-reset function of an external processor.
All power management functions can be configured using pin configuration techniques or through the I2C/SMBus interface. Monitoring parameters can also be preconfigured to provide alerts for specific conditions.
Multimode Pins To simplify circuit design, the zl2106 features patented multimode pins that allow users to easily configure many aspects of the device without programming. Most power management functions can be configured using these pins. Multimode pins can respond to four different connections. These pins are set at power-up or by issuing the pmbus restore command pin strip. This is the easiest way as no additional components are required. Using this method, each pin can assume one of three possible states: low, on, or high. These pins can be connected to the V2P5 pin for a logic high setting as this pin provides a regulated voltage higher than 2V. One of three settings can be selected using a single pin.

Resistor Setup This method allows for a larger adjustable range when connecting a finite value resistor (within the specified range) between the multimode pin and the SGND.
Using the standard 1% resistor value and using only the fourth E96 resistor value, the device can reliably identify the resistor value connected to the pin while eliminating errors associated with resistor accuracy. Up to 31 unique options can be selected using one resistor.
I2C/SMBus method
The zl2106 functionality can be configured via the i2c/smbus interface using standard pmbus commands. Additionally, any value configured using the pin strip or resistor setup methods can also be reconfigured and/or verified via i2c/smbus.
smbus device address and vout_max are the only parameters that must be set by external pins. All other device parameters can be set via i2c/smbus. The device address is set using the sa pin. Vout_max is determined to be 10% greater than the voltage set by the VSET pin.
Resistor pin strips are recommended for all available device parameters for a safe initial power-up before storing the configuration via I2C/SMBus. For example, this can be accomplished by pin tying the undervoltage lockout threshold (using the SS pin) to a value greater than the expected input voltage, preventing the device from enabling until the configuration file is loaded.
Power Conversion Functional Description Internal Bias Regulator and Input Power Connections
The ZL2106 employs three internal low dropout (LDO) regulators to provide bias voltage to the internal circuitry, allowing it to operate from one input supply. The internal bias regulator is as follows:
vr:vr ldo provides a stable 7v bias supply for the high side mosfet driver circuit. It is powered by the vdds pin and internally provides bias current. The VR pin needs a 4.7µF filter capacitor. The vdds pin directly supplies power to the low voltage mosfet driver circuit.
VRA: The VRA LDO provides a regulated 5V bias supply for current sense circuits and other analog circuits. It is powered by the vdds pin and internally provides bias current. A 4.7µF filter capacitor is required at the VRA pin.

V2P5: The V2P5 LDO provides an adjustable 2.5V bias supply for the main controller circuit. It is powered by the VRA LDO and internally provides bias current. A 10µF filter capacitor is required at the V2P5 pin.
VR and VR pins should not be connected to any other pins when the input power supply (VDD) is higher than 7.5V. Only one filter capacitor should be connected to these pins. Due to the voltage drop associated with the VR and VRA biasing regulators, the VDDs pins must be connected to these pins for designs operating from supplies below 7.5V. Figure 14 illustrates the connections required in all cases.
NOTE: The internal bias regulators, VR and VRA, are not outputs designed to power other circuits. Do not connect external loads to these pins. Only multimode pins can be connected to the V2P5 pin for logic high settings.
High Side Driver Booster Circuit The gate drive voltage for the high side mosfet driver is generated by a floating bootstrap capacitor cb, when the lower mosfet (ql) is turned on, the sw node is pulled to ground, the capacitor is biased from the internal vr regulator through the diode db Charge. When the Ql is off and the upper mosfet (qh) is on, the SW node is pulled to vddp and the voltage on the bootstrap capacitor is boosted to about 6.5v above vddp to provide the necessary voltage to power the high side driver. An internal Schottky diode is used with CB to help maximize the high-side drive supply voltage.
OUTPUT VOLTAGE SELECTION The output voltage can be set to any voltage between 0.6v and 5.0v, provided the input voltage is higher than the desired output voltage by an amount sufficient to prevent the unit from exceeding its maximum duty cycle specification. Using the pin-strap method, VOUT can be set to one of the three standard voltages shown in Table 2.

Good power (pg)
The ZL2106 provides a Power Good (PG) signal indicating that the output voltage is within the specified tolerance of its target level and no fault conditions exist. By default, the PG pin will be asserted if the output is within +15%/-10% of the target voltage. These limits can be changed via the i2c/smbus interface.
The pg latency period is the time from when all conditions for asserting the pg are met until the pg pin is actually asserted. This feature is typically used in place of an external reset controller to signal the power supply its target voltage before enabling any power supply circuits. By default the zl2106 pg latency is set to 1ms, this can be changed using the i2c/smbus interface as described by an2033.
Switching Frequency and Phase Locked Loop
The ZL2106 uses an internal phase-locked loop (PLL) to clock the internal circuits. pll can be driven by an external clock source connected to the sync pin. When using the internal oscillator, the sync pin can be configured as a clock source for other zilker lab equipment.

When the sync pin is configured as an output (cfg pin is held high), the device will run from its internal oscillator and drive the resulting internal oscillator signal (preset at 400kHz) onto the sync pin so that Other devices can sync with it. In this mode, the sync pins are not checked for an incoming clock signal.
Configuration B: Configuration B: Sync Input

SYNC PIN CONFIGURATION When the SYNC pin is configured as an input (the cfg pin is clamped low), the device will automatically check for an external clock signal on the SYNC pin each time the EN pin is asserted. The internal oscillator will then be synchronized to the rising edge of the external clock. The incoming clock signal must be in the range of 200kHz to 1MHz with a minimum duty cycle and must be stable when the EN pin is asserted. The external clock signal must also have the necessary performance requirements.
In the event of loss of external clock signal, the output voltage may show transient over/overshoot. If this happens, the ZL2106 will automatically switch to its internal oscillator and switch at a frequency close to the previous input frequency.
Configuration C: Sync Auto-Detect When the sync pin is configured in auto-detect mode (the cfg pin remains on), the device will automatically check the clock signal on the sync pin after asserting enable. If a valid clock signal is present, the ZL2106 oscillator will be synchronized to the rising edge of the external clock (see synchronization input description).
If no input clock signal is present, the zl2106 will configure the switching frequency based on the state of the listed sync pins. In this mode, the ZL2106 will only read the sync pin connections during the startup sequence. Changes to the sync pin connections will not affect the FSW until the power supply (VDD) is cycled off and on again.

Power Management Function Description Input Undervoltage Lockout Input undervoltage lockout (UVLO) prevents the ZL2106 from operating when the input falls below a preset threshold, indicating that the input power is outside its specified range. According to Table 6, the UV threshold (Vuvlo) can be set to 4.5V or 10.8V using the SS pin.
The uvlo voltage can also be set to any value between 2.85v and 16v via the i2c/smbus interface.
In the event of an input undervoltage fault, the device can respond in a number of ways:
1. Continue running without interruption.
2. Continue running for the given delay time and shut down if the fault persists. The device will remain powered off until instructed to restart.
3. Initiate an immediate shutdown until the fault clears. The user can choose a specific number of retries.
The default response to uvlo failure is to shut down the device immediately. Details on how to configure UVLO thresholds or select specific UVLO fault response options via i2c/smbus interface Output overvoltage protection
The ZL2106 provides internal output overvoltage protection circuitry that can be used to protect sensitive load circuits from voltages above their specified limits. A hardware comparator is used to compare the actual output voltage (seen on the vsen pin) to a threshold set 15% above the target output voltage (default setting). If the vsen voltage exceeds this threshold, the PG pin will be de-asserted and the device can then respond in any of the following ways:
1. Initiate an immediate shutdown until the fault clears. The user can choose a specific number of retries.
2. Turn off the high-side mosfet and turn on the low-side mosfet. The low side mosfet remains on until the device attempts to restart. The default response to an overvoltage fault is an immediate shutdown. For continuous overvoltage protection when running from an external clock, the only allowed response is an immediate shutdown. Details on how to select specific overvoltage fault response options via I2C/SMBus Output Pre-Bias Protection An output pre-bias condition exists when an externally applied voltage is present on the output of the power supply before the power supply's control IC is enabled. Some applications require that the converter is not allowed to sink current during startup if a pre-bias condition exists at the output. The ZL2106 provides pre-bias protection by sampling the output voltage before starting the output ramp.
If there is a pre-bias voltage lower than the target voltage after the pre-configured delay period, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. The output voltage is then ramped to the final regulated value at the ramp rate set by the ss pin.
The actual ramp time of the output from the pre-bias to the target voltage will depend on the pre-bias, but the total elapsed time from the expiration of the delay period until the output reaches the target value will match the pre-configured ramp time.
If there is a pre-bias voltage higher than the target voltage after the pre-configured delay period, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled which ideally produces a pre-bias The pwm duty cycle of the voltage.
Once the pre-configured soft-start ramp period is over, the PG pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). The PWM will then adjust its duty cycle to match the original target voltage and the output will drop to the preconfigured output voltage

Pre-Biased Output Response Voltage In the presence of pre-bias above the overvoltage limit, the device will not initiate a start-up sequence and an overvoltage fault condition will be declared. In this case, the device will respond according to the selected output overvoltage fault response method.
Output Overcurrent Protection The ZL2106 protects the power supply from damage if the output is shorted to ground or an overload condition is imposed on the output. Once the current limit threshold is selected (see "Current Sensing and Current Limit Threshold Selection" on page 19), the user can determine the desired course of action based on fault conditions. The following overcurrent protection response options are available:
1. Initiate a shutdown and attempt an infinite restart, with a preset delay period between attempts.
2. Initiate a shutdown and attempt a preset number of restarts within a preset delay time between attempts.
3. Continue to run for the given delay time and shut down if the fault persists.
4. Continue working through the fault (this may cause permanent damage to the power supply).
5. Immediately shut down.
6. The default response to an overcurrent fault is to shut down the device immediately. See application note AN2033 for details on how to select specific overcurrent fault response options via I2C/SMBus.
Thermal overload protection
The ZL2106 includes an on-chip thermal sensor that continuously measures the internal temperature of the mold and shuts down the device when the temperature exceeds preset limits. The factory default temperature limit is set to +125°C, but the user can set this limit to another value if desired. See application note AN2033 for details. Note that setting a higher thermal limit via the I2C/SMBus interface may cause permanent damage to the device. Once the device is disabled due to an internal temperature fault, the user can choose one of several fault response options:
1. Initiate a shutdown and attempt an infinite restart, with a preset delay period between attempts.
2. Initiate a shutdown and attempt a preset number of restarts within a preset delay time between attempts.
3. Continue to run for the given delay time and shut down if the fault persists.
4. Continue working through the fault (this may cause permanent damage to the power supply).
5. Immediately shut down.
If the user has configured the device to restart, the device will wait a preset delay time (if configured to do so) and then check the device temperature. If the temperature has dropped below a threshold of approximately +15°C below the selected temperature fault limit, the device will attempt to restart. If the temperature still exceeds the fault limit, the device will wait the preset delay time and try again.
The default response to a temperature fault is to shut down the device immediately. See application note AN2033 for details on how to select specific temperature fault response options via I2C/SMBus.
Voltage Tracking Many high-performance systems place stringent requirements on the turn-on sequence of supply voltages. This is especially true when powering FPGAs, ASICs, and other advanced processor devices that require multiple supply voltages to power a single chip. In most cases, the I/O interface operates at a higher voltage than the core, so according to the manufacturer's specifications, the core supply voltage must not exceed the I/O supply voltage.
Voltage tracking protects these sensitive integrated circuits by limiting the differential voltage between multiple power supplies during power up and power down. The zl2106 integrates a lossless tracking scheme that allows its output to track the voltage applied to the vtrk pin without the need for additional components. The vtrk pin is an analog input that configures the voltage applied to the vtrk pin to be used as a reference for device output regulation when tracking mode is enabled.
1. Coincidence. This mode configures the ZL2106 to ramp up its output voltage at the same rate as the voltage applied to the VTRK pin.
2. Ratio method. This mode configures the ZL2106 to boost its output voltage at a rate that is a percentage of the voltage applied to the VTRK pin. The default setting is 50%, but external resistors can be used to configure different tracking ratios.

The master device in a tracking group is defined as the device with the highest target output voltage in the group. This master device will control the ramp rate of all tracking devices and is not configured in tracking mode. A delay of at least 10ms must be configured into the master using the ss pin, and the user can also configure a specific ramp rate using the ss pin.
Any device configured for tracking mode will ignore its soft-start delay and ramp time settings (SS pin) and its output will assume the on/off characteristics of the reference voltage on the VTRK pin. All enable pins in a trace group must be connected together and driven by a single logic source.
Tracking mode can also be configured via the i2c/smbus interface using the track_config pmbus command.
voltage margin
The ZL2106 provides an easy way to change its output above or below its rated voltage setting to determine if the load device can operate within its specified supply voltage range. The mgn command is set by driving the mgn pin or through the i2c/smbus interface. The MGN pin is a continuously monitored three-level input that can be directly driven by processor I/O pins or other logic-level outputs.
When the mgn command is set high, the output of the zl2106 will be forced above its nominal setpoint, and when the mgn command is set low, the output will be forced below its nominal setpoint. The default margin limit of Vnom ±5% is preloaded at the factory, but the margin limit can be modified through the I2C/SMBus interface to be as high as Vnom+10% or as low as 0V, where Vnom is the nominal output determined by the VSET pin Voltage setpoint. A safety feature prevents the user from configuring the output voltage to exceed vnom+10% under any circumstances.