The AD7870 /AD7875/AD7876 have several interface options. They offer two modes of operation and three data output formats. Fast data access times allow direct connection to most microprocessors including DSP processors.

Parallel read interface

Figure 1, Figure 2, and Figure 3 show the interfaces of the ADSP-2100, TMS32010 , and TMS32020 DSP processors. The ADC operates in Mode 1 with parallel reads from all three interfaces. An external timer controls conversions that are initiated asynchronously with the microprocessor. The adc busy/int interrupts the microprocessor at the end of each conversion. Read the conversion result from the adc using the following command:

ADSP-2100: MR0=dm (analog-to-digital converter)

tms32010: input d, adc

tms32020: input d, adc

MR0 = ADSP-2100 MR0 register

D = data memory address

ADC=AD7870/AD7875/AD7876 address

Some applications may require that the conversion be initiated by the microprocessor rather than an external timer. One option is to decode the convst signal from the address bus so that a write operation to the ADC starts the conversion. As before, the data is read at the end of the conversion. Note: Read operations must not be attempted during conversion.

Double-byte read interface

68008 interface

Figure 4 shows the 8-bit bus interface-processor of the MC68008 Micro. For this interface, the 12/8/CLK input is tied to 0 V and the DB11/HBEN pin is driven by the microprocessor least significant address bits. Conversion start control is provided by the microprocessor. In this interface example, a MOVE instruction from an ADC address initiates a conversion and reads the conversion result.

mobile analog-to-digital converter

ADC=AD7870/AD7875/AD7876 address

d0=68008 d0 register

This is a two-byte read instruction. when reading it for the first time. Busy operation, combined with CS, forces the microprocessor to wait for ADC conversions. At the end of the conversion, the ADC low byte (DB7–DB0) is loaded into D15–D8 in the D0 register, and the ADC high byte (DB15–DB7) is loaded into the D0 register in bits D7–D0. The following rotate instruction to the d0 register swaps the high and low bytes into the correct format. R0L=8, D0. Note that when executing the above two-byte read instruction, the wait state is only inserted during the first read operation, not during the second read operation.

serial interface

Figure 5, Figure 6, Figure 7, and Figure 8 show the AD7870/AD7875/AD7876 configured for a serial interface. In all four interfaces, the ADC is configured for Mode 1 operation. The interface shows a timer that drives the convst input, but can be generated from decoded addresses if desired. The SCLK, SDAT, and SSTRB are open-drain outputs. Buffering is recommended if these are required to drive capacitive loads in excess of 35 pF.

DSP56000 serial interface

Figure 26 shows the serial interface between the AD7870/AD7875/AD7876 and the DSP56000. The interface is configured as two-wire system, and the ADC is configured as discontinuous clock operation (12/8/CLK=0V). The DSP56000 is configured for normal mode asynchronous operation with a gated clock. It is also set to a 16-bit word with SCK and SC1 as inputs and the FSL control bit set to 0. In this configuration, the DSP56000 assumes valid data on the first falling edge of SCK. Since the ADC provides valid data on this first edge, no strobe or framing of data is required. When the ADC is not performing conversions, SCLK and SData are gated off. During the conversion process, the data is valid at the output of the ADC on sdata and is recorded into the receive data shift register of the DSP56000. When this register receives 16-bit data, it generates an internal interrupt on the dsp56000 to read the data from the register.

The DSP56000 and AD7870/AD7875/AD7876 can also be configured for continuous clock operation (12/8/CLK=-5 V). In this case, the DSP56000 needs a strobe to indicate when the data is valid. The SSTRB output of the ADC is inverted and applied to the SC1 input of the DSP56000 to provide this strobe. All other conditions and connections are the same as for gated clock operation.

NEC7720 /77230 Serial Interface

The serial interface between the AD7870/AD7875/AD7876 and the NEC7720 is shown in Figure 27. In the interface shown, the ADC is configured for continuous clock operation. This can be changed to a non-continuous clock by simply connecting the ADC's 12/8/CLK input to 0V while leaving all other connections the same. The NEC7720 expects valid data on the rising edge of the SCK input, so an inverter is required on the SCLK output of the ADC. The NEC7720 is configured as a 16-bit data word. Once the si register of the nec7720 receives 16-bit data, an internal interrupt is generated to read the content of the si register. The NEC77230 interface is similar to the one just outlined for the NEC7720. However, the clock input of the nec77230 is siclk. Also, an inverter is not required between the ADC sclk output and this siclk input because the nec77230 assumes that data on the falling edge of siclk is valid.

tms32020 serial interface

Figure 7 shows the serial interface between the AD7870/AD7875/AD7876 and the tms32020. The AD7870/AD7875/AD7876 are configured for continuous clock operation. Note that if the ADC is configured with a non-continuous clock, the ADC will not be able to interface with the tms32020 properly. During the conversion process, the data is clocked into the data receive register (drr) of the tms32020. As with the previous interface, when the tms32020 receives a 16-bit word, it generates an internal interrupt to read data from drr.

ADSP-2101/ADSP-2102 Serial Interface

Independent operation

The AD7870/AD7875/AD7876 can be used for stand-alone operation in their Mode 2 parallel interface mode. In this case, the conversion is initiated by a pulse to the ADC CS input. This pulse must be longer than the conversion time of the ADC. This busy output is used to drive the rd input. Data is latched from the ADC DB0–DB11 outputs to an external latch on the rising edge of busy.

Independent operation

The AD7870/AD7875/AD7876 can be used in their Mode 2, parallel interface mode of stand-alone operation. In this case, the conversion is initiated by a pulse to the ADC CS input. This pulse must be longer than the conversion time of the ADC. This busy output is used to drive the rd input. Data is latched ADC DB0–DB11 is output to the busy edge of the external latch on rising.

application information

A good printed circuit board (PCB) layout is just as important for achieving high-speed analog-to-digital performance as the overall circuit design itself. The designer must pay attention to the noise in the ADC itself and in the previous analog circuit. Switch-mode power supplies are not recommended because switching spikes cause noisy code transitions through the comparator. Other causes of concern are ground loops and digital feedback from microprocessors. These are all factors that affect any ADC, and proper pcb layout to minimize these effects is the key to getting the best performance.

layout hints

Make sure that the layout of the printed circuit board separates the digital and analog signal lines as much as possible. Be careful not to run any digital tracks next to the analog signal tracks. Protect (screen) analog input with agnd.

Establish a single point analog ground (star ground) separate from the logic system ground at the AGND pin, or as close to the ADC as possible. Connect all other grounds and the AD7870/AD7875/AD7876 DGND to this single analog ground. Do not connect any other digital ground to this analog ground.

Low-impedance analog and digital power supply commons are critical for low-noise operation of the ADC, so keep the foil width of these tracks as wide as possible. The use of a ground plane minimizes impedance paths while also protecting analog circuits from digital noise. The circuit layout has analog and digital ground planes that are kept separate and connected together only at the AD7870/AD7875/AD7876 AGND pins.

noise

Keep the input signal line to V and the signal return line from Agnd as short as possible to minimize input noise coupling. In applications where this is not possible, use a shielded cable between the source and the ADC. Keep the ground circuit impedance as low as possible, because the ground potential difference between the signal source and the ADC shows up as an erroneous voltage in series with the input signal. in external dimensions

Control dimensions are in inches; millimeter dimensions (in parentheses) are rounded to the nearest inch equivalent, and corner leads can be configured as solid leads or half leads. ; for informational purposes only, not for design.

(in parentheses) are rounded inch equivalents; for informational purposes only, not for design.

Control dimensions are in inches; millimeter dimensions; (in parentheses) are rounded inch equivalents; for informational purposes only, not for design.

Conforms to JEDEC Standard MS-013-AD Control dimensions are in millimeters; dimensions in inches; (in parentheses) are rounded millimeter equivalents; for informational purposes only, not for design.