Features

Low -voltage noise: 1.1nv/√Hz

Input voltage noise: 80nvpp (0.1Hz to 10Hz)

[ 123] THD+N: - 136DB (g u003d 1, f u003d 1kHz)

offset voltage: 125μV (maximum)

unity-gain stable [ 123]

Application

lock phase ring filter

low noise, low power signal processing

16 Bit ADC driver

DAC output amplifier

Affective filter

Low noise meter amplifier

] Ultrasonic amplifier

Professional audio front amplifier

Low noise frequency synthesizer

infrared detector Amplifier

Water Listener amplifier

detector amplifier

Medicine

123] OPA211 series precision computing amplifier achieves very low 1.1NV/√Hz noise density, and the power current is only 3.6mA. The series also provides rails to swing, maximizing the dynamic range.

Very low voltage and low -current noise of the OPA211 seriesThe sound, high -speed and wide output width make these devices the best choice for PLL applications Central circuit filter amplifiers.

In the precision data collection application, the OPA211 series operational amplifier provides 700ns stability to 16 -bit accuracy during the 10V output swing period. This communication performance plus only 125 μV's offset and temperature drift of 0.35 μV/° C, making OPA211 very suitable for driving high precision 16 -bit modulus converters (ADC) or cushioning high -resolution digital modulus converter (DAC). Output.

Typical features TA+25 ° C, vs u003d ± 18V, RL u003d 10K , unless otherwise explained. ] Application information

OPA211 and OPA2211 are the operating amplifiers with stable unit gain and very low accuracy. The application of noise or high impedance power supply requires the degraded capacitor pins near the device. In most cases, 0.1 μF capacitors are enough. Figure 44 shows the simplified schematic diagram of OPA211. The chip uses the SIGE bipolar process and contains 180 transistors.

Working voltage

OPA211 series operational amplifier can work within the range of ± 2.25V to ± 18V, while maintaining excellent performance. OPA211 series can be the minimum+4.5V and power supply between the power supplyWorking in the case of+36V. However, some applications do not require equal positive and negative output voltage. For the OPA211 series, the power supply voltage does not need to be equal. For example, the positive power supply can be set to+25V, and the negative electrode power supply is set to -5V, and vice versa.

The co -mode voltage must be kept within the specified range. In addition, the key parameters are guaranteed within the specified temperature range, and TA u003d -40 ° C to+125 ° C. The typical feature shows the parameters of significantly changes with the working voltage or temperature.

Input protection

The input terminal of OPA211 to prevent excessive differential voltage through the back -to -back diode, as shown in Figure 45. In most circuit applications, there are no consequences of input protection circuits. However, in a low -gain or G u003d 1 circuit, because the output of the amplifier cannot respond enough to the input slope, the fast slope input signal can make these diode offset forward. Typical features Figure 32 illustrate this impact. If the input signal is fast enough to generate this positive bias condition, the input signal current must be limited to 10mA or below. If the input signal current is not restricted by in good condition, the input series resistor can be used to limit the input current of the signal. The input series resistor reduces the low noise performance of OPA211 and discusses the noise performance part of this data table. Figure 45 shows an example of a current -limiting feedback resistor.

Close

Close (enabled) of OPA211's positive power supply voltage. Effective high value will disable the operation amplifier. Effective high voltage is defined as the (V+)-0.35V that applied the positive electrode power supply to the stop selling. Effective low voltage is defined as (V+)-3V at the feet of the positive power supply. For example, when the VCC is ± 15V, the device starts at 12V or below. The device is disabled at 14.65V or above. If you use a dual power supply or split power supply, you should pay attention to ensuring effective high input or effective low input signals correctly refer to the positive power supply voltage. This pin must be connected to an effective high or low voltage or driver instead of leaving a way. Enable and disable time are provided in the typical feature part (see Figure 41 to 43). When disabled, the output assumes a high impedance state.

Noise Performance

FIG. 46 shows the general circuit noise of the total circuit noise of the op amp sources in the unit gain configuration (no feedback resistance network, so there is no additional noise contribution). Two different operational amplifiers display and general circuit noise calculation. OPA211 has a very low voltage noise, making it an ideal choice for low source impedance (less than 2K ). A similar precision computing amplifier, OPA227, has high voltage noise, but lower current noise. It is in medium -sources (10K to 100K ) It provides excellent noise performance. At 100K above, FET enters op amp, such as OPA132 (very low current noise) can provide better performance. The formula in FIG. 46 is used to calculate the general circuit noise. Note that EN u003d voltage noise, IN u003d current noise, RS u003d source impedance, K u003d Bolzman constant u003d 1.38 × 10–23 j/k, T is temperature, unit: Kaishi.

Basic noise calculation

The design of the low noise computing amplifier circuit needs to carefully consider various possible noise factors: noise from the signal source, in the operation amplifier The noise generated and noise from the feedback network resistor. The total noise of the circuit is a square root and combination of all noise components.

The resistance part of the source impedance generates the heat noise of proportion to the square root of the resistance. This function is shown in Figure 46. The source impedance is usually fixed; therefore, the choice of op amp and feedback resistance to minimize the contribution of their total noise.

FIG. 46 describes the total noise of different source impedances of the op amp under the configuration of the unit gain (there is no feedback resistance network, so there is no additional noise contribution). The operation amplifier itself generates voltage noise components and current noise components. The voltage noise is usually modified as the time to change the component of the bias voltage. The current noise is modeled to the time variable in the input bias current, and the voltage component of the noise is generated with the source resistance reaction.

Therefore, the minimum noise computing amplifier given by a given application depends on the source impedance. For low -source impedance, current noise can be ignored, and voltage noise usually dominates. For high -source impedance, current noise may dominate.

FIG. 47 illustrates the configuration of the inverter and non -inverter computing amplifier circuit. In the configuration of the gains, the feedback network resistance will also produce noise. The current noise of the amplifier and the feedback resistor reaction to generate additional noise components. The feedback resistance value can usually be selected so that these noise sources can be ignored. The total noise equation of the two structures is given.

Total harmonic distortion measurement

OPA211 series operational amplifier has excellent distortion characteristics. Throughout the audio range, when 20Hz to 20kHz, the load was 600 when THD+noise below 0.0002%(g u003d+1, vout u003d 3VRMS).

The distortion generated by the OPA211 series operations amplifier is lower than the measurement limit of many commercial distortion analyzers. However, the special test circuit shown in FIG. 48 can be used to expand measurement capabilities.

The operational amplifier distortion can be considered as an internal error source, and you can refer to the input. Figure 48 shows a circuit that causes 101 times distorted by the operation amplifier distortion than the general distortion of the computing amplifier. In otherAdding R3 to the standard non -easier amplifier configuration will change the feedback coefficient or noise gain of the circuit. The closed -loop gain is unchanged, but the feedback that can be used for error correction is reduced by 101 times, which increases the resolution by 101 times. Note that the input signals and loads of the computing amplifier are the same as the traditional feedback without R3. The value of R3 should be kept smaller to minimize its impact on distortion measurement.

The effectiveness of this technology can be verified by repeating measurement under high gain and/or high frequency. Among them, distortion is equipped with equipment within the measurement capacity range of testing. Measuring this data table uses the audio precision system dual distortion/noise/noise. The production of the analyzer greatly simplifies the repeated measurement. However, the measurement technology can be executed by manual distortion measuring instruments.

Excessive electrical stress

Designers often ask the capacity of computing amplifiers to withstand excessive electrical stability. These problems are often concentrated on the device input, but may involve the power supply voltage pins and even output pins. Each different pins function has the electrical stability limit determined by the voltage breakdown characteristics of a specific semiconductor manufacturing process and a specific circuit connected to the pin. In addition, internal electrostatic discharge (ESD) is protected in these circuits to prevent an ESD incident that occurs before and in the process of product assembly.

It helps better understand the correlation between this basic ESD circuit and its electrical excessive stress events. The ESD circuit schematic diagram contained in OPA211 (represented by the dotted line area). The ESD protection circuit includes several current control diode. These diode connect from the input and output pin and return to the internal power cord. There, they will be placed in the absorption device inside the operating system. This protective circuit remains inactive during the operation of the normal circuit.

The ESD event will generate a high -voltage pulse with a short duration. When it discharge through semiconductor devices, the pulse is converted into a short duration and large current. pulse. The ESD protective circuit design is used to provide a current circulation around the core of the computing amplifier to prevent it from being damaged. The energy absorbed by the protective circuit was subsequently lost in the form of heat.

When one ESD voltage is formed on the pin of two or more amplifiers, the current flows over one or more to the diode. According to the path of the current, the absorption device may be activated. The trigger voltage or threshold voltage of the absorption device is higher than the normal operating voltage of OPA211, but it is lower than that of the breakdown voltage level of the device. Once this threshold is exceeded, the absorption device will start quickly and keep the voltage on the power rail at the level of safety.

As shown in Figure 49, when ESD is applied to the circuit, it is connected to the circuit. However, when the external voltage exceeds the operating voltage range of the given pin, this may occur. If this happens, there are risks that some internal ESD protection circuits may be biased and transmitted. Any current current isIt is rarely involved in the absorption device through the directional diode path.

FIG. 49 describes a specific example, where the input voltage vin exceeds 500 millivolttoons (+vs) or more. Most of the situations in the circuit depends on the power characteristics. If+vs can absorb current, one of the upper input to the diode to guide the current to+and over -to -+with the higher and higher of the vehicle recognition number (VIN), the current level may become higher and higher. Therefore, the data table specifications are recommended to limit the input current to 10mA.

If the power supply cannot absorb the current, VIN can start to provide the current to the computing amplifier, and then take over as a positive power supply voltage source. The risk in this case is that the voltage may rise to the level that exceeds the absolute maximum rated value of the operation amplifier. In extreme but rare cases, the absorption device will be triggered when+vs and -vs. If this incident occurs, the DC path is established between+VS and -VS power. The power consumption of the absorption device is quickly exceeded, and the extreme internal heating will destroy the operational amplifier.

Another common problem is that when the power+vs and/or -vs are 0V, if the input signal is applied to the input terminal, what will happen when the amplifier will happen. Similarly, this depends on the power characteristics of the level at the level of 0V or lower than the amplitude of the input signal. If the power supply is displayed as high impedance, the power supply current of the computing amplifier can be provided by the input source through the current control the diode. This state is not a normal partial pressure; the amplifier is likely to not work properly. If the power impedance is low, the current to the diode may become quite high. The current level depends on the capacity of the input source transmission current and any resistance in the input path.

Hot factors

One of the main problems of all semiconductor devices is knot temperature (TJ). The most obvious consideration is to ensure that TJ will never exceed the absolute maximum rated value specified by the device. However, in addition to protecting the equipment from the protection equipment from damage, the addressing equipment has other benefits. Even if it is moderately improved, the performance of the operation amplifier will be reduced, and the error related to temperature will accumulate. Understand the power generated by the device in a specific application, and evaluate the effects of the thermal effect on the error tolerance, which helps better understand the system performance and heat dissipation needs. For dual -channel products, the worst situation of the two channels must be determined. Products with hot pads (DFN and PowerPad devices) provide the best thermal conduction away from knot; see the thermal resistance parameters (θJp) from the pad to the pad in the electrical characteristics part. Using a package with hot pads improves heat dissipation. The device realizes its best performance through a careful circuit board and system design. These designs take into account the thickness of the plate thickness, metal layer, component spacing, airflow, and board direction.

DFN package

OPA211 is provided in the DFN-8 package (also known as SON). DFN packaging is a kind of QFN packaging, which is only two in the bottom of the packaging.side. This lead -free packaging has expanded the circuit board space to the maximum extent, and enhances thermal characteristics and electrical characteristics through a bare pad.

DFN package is very small in physical, the route area is smaller, the thermal performance is improved, and the performance of the electrical performance has also been improved. In addition, there is no external lead to eliminate the problem of bending.

DFN packaging can be easily installed with standard printing circuit board (PCB) assembly technology. Please refer to the application instructions QFN/SON PCB Annex (SLUA271) and Application Report Quad Flatpack No Drawing Logic encapsulation (SCBA017).

The exposed lead frame mold pad at the bottom of the packaging must be connected to V -. Welding hot pads can improve heat dissipation capacity and achieve specific equipment performance.

DFN layout guide

DFN packaged naked lead framework mold pads should be welded on the hot pads on the PCB. At the end of this data table, there is a mechanical chart of the display layout example. According to the requirements of the assembly process, the layout may be improved. The mechanical drawings at the end of this data table list the physical dimensions of packaging and pads. The five holes in the platform pattern are optional, which is used to connect the radiating pores of the leading frame of the lead frame and the PCB heat sink area.

In temperature circulation, keys, packaging cutting, and similar board tests, welded exposed pads have significantly improved board -level reliability. Even in low -power applications, naked pads must be welded to PCB to provide structural integrity and long -term reliability.

General precautions for the design of the power board

OPA2211 provides a thermal enhancement SO-8 PowerPad package. This packaging is installed on it with a lower -loading frame, as shown in Figure 50 (a) and Figure 50 (b). This layout causes the lead frame to be exposed to the bottom of the packaging, as shown in Figure 50 (C). The thermal pads directly contact the mold; therefore, it can obtain excellent thermal performance by providing a good heat path away from the hot pad.

PowerPad package allows assembly and thermal management at the same time in a manufacturing operation. During the surface of the surface (when welding), the thermal pads must be welded to the copper area below the packaging. By using the heat path in this copper area, the heat can be transmitted from the package to the ground layer or other heat dissipation devices. Always need to welded PowerPad to the printing circuit board (PCB), even in low -power applications. This technology provides necessary thermal connections and mechanical connections between the leading frame of the lead framework and PCB.

The power board must be connected to the most negative power voltage (V-) on the device.

1. Prepare the PCB mode with the top surface. It should be eclipsed and etching hot pads.

2. Recommended holes in the thermal pad area. SO-8 DDAThe encapsulated ideal thermal pads and thermal hole mode can be found in the technical briefing PowerPad thermal enhancement package (SLMA002). The diameter of these holes should be 33mm. Keep them very small, so that the weld core is not a problem during the period of the pores. Example hot landing mode Mechanical map is attached to the end of this data table.

3. Set additional hole in any position of the thermal plane outside the thermal pad area to help dissipate the heat generated by OPA2211 SO-8. These additional holes may be larger than the pores with 13 dense ears in the front diameter of the hot pad. They can be larger because they are not welded with hot pads; therefore, core suction is not a problem.

4. Connect all holes to the same internal plane as the V-pin voltage.

5. When connecting these holes to the internal plane, do not use a typical abdomen or wheel spoke connection method. The network connection has a high thermal resistance connection, which helps to slow the heat transfer during the welding process. This configuration makes it easier to weld the pores with a flat connection. However, in this application, in order to achieve the most effective heat transfer, low thermal resistance is required. Therefore, the holes under the OPA2211 PowerPad should be connected to the internal plane and a complete connection around the entire circle of electroplated holes.

6. The top welded mask should expose six holes in the packing terminal and thermal pads. The welding mask at the bottom should cover the hole in the hot pad area. This cover can prevent the welded from being pulled away from the thermal pads during the return welding process.

7. Apply the tiny paste to the exposed thermal pad area and all IC terminals.

8. After preparing these preparation steps, just place OPA2211 SO-8 integrated circuits in place, and use the chip as a standard surface-installed component for welding backwing operation. This preparation work can make the parts correctly installed.