General Instructions

The AD7870 /AD7875/AD7876 are fast, complete 12-bit analog-to-digital converters (ADCs). These converters consist of a track-and-hold amplifier, an 8µs successive approximation adc, a 3v buried zener reference, and multifunction interface logic. The ADC has an independent internal clock that is laser trimmed to ensure precise control of conversion times. No external clock timing components are required; the on-chip clock can be overridden by an external clock if desired.

These sections provide a choice of three data output formats: single, parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus access times and standard control inputs ensure easy interfacing with modern microprocessors and digital signal processors.

All parts are powered by ±5 V supplies. The AD7870 and AD7876 accept input signal ranges of ±3 V and ±10 V, respectively, while the AD7875 accepts a unipolar input range of 0 V to +5 V. These parts can convert full power signals up to 50 kHz.

The AD7870/AD7875/AD7876 have dc accuracy specifications such as linearity, full scale, and offset error. In addition, the AD7870 and AD7875 fully specify dynamic performance parameters, including distortion and signal-to-noise ratio.

These parts are available in 24-pin, 0.3-inch wide, plastic or hermetically sealed dual-in-line packages (DIPs). The AD7870 and AD7875 are available in a 28-pin plastic leaded chip carrier (PLCC), while the AD7876 is available in a 24-pin small outline (SOIC) package.

Product Highlights

1. Complete the 12-bit ADC on the chip. The AD7870/AD7875/AD7876 provide all the functions required for analog-to-digital conversion and combine a 12-bit ADC with an internal clock, track-and-hold amplifier, and reference signal on a single chip.

2. Dynamic specification of digital signal processor users. The AD7870 and AD7875 are fully specified and tested for ac parameters, including signal-to-noise ratio, harmonic distortion, and intermodulation distortion.

3. Fast microprocessor interface. A data access time of 57ns makes these parts compatible with modern 8- and 16-bit microprocessors and digital signal processors. Key digital timing parameters are tested and guaranteed over the entire operating temperature range.

Rotating speed. C

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Converter Details

The AD7870/AD7875/AD7876 is a complete 12-bit ADC requiring no external components other than power supply decoupling capacitors. It consists of a 12-bit successive approximation ADC based on a fast stabilizing voltage output DAC, a high speed comparator and SAR, a track-and-hold amplifier, a 3V buried zener reference, a clock oscillator and control logic.

internal reference

The AD7870/AD7875/AD7876 have an on-chip temperature compensated buried Zener reference that is factory trimmed to 3 V ±10 mV. Internally, it provides the DAC reference and dc bias required for bipolar operation (AD7870 and AD7876). A reference output is available (ref out) capable of delivering up to 500µA to an external load.

Maximum Recommended Capacitance at Reference Output

Normal operation is 50 pf. If the reference needs to be used external to the ADC, it should be separated using a 200 Ω resistor in parallel with a 10µF tantalum capacitor and a 0.1µF ceramic capacitor. These decoupling components are used to remove voltage spikes caused by the ADC's internal operations.

The reference output voltage is 3 V. For applications using the AD7875 or AD7876, a 5 V or 10 V reference may be required. The diagram shows how to scale the 3V reference to provide a 5V or 10V external reference.

Track Hold Amplifier

The track-and-hold amplifier on the analog input of the AD7870/AD7875/AD7876 allows the ADC to accurately convert the input frequency to 12-bit accuracy. The input bandwidth of the track-and-hold amplifier is much larger than the Nyquist rate of the ADC, even when operating at its maximum throughput rate. A cutoff frequency of 0.1 dB typically occurs at 500 kHz. The track-and-hold amplifier obtains a 12-bit precision input signal in less than 2µs. The total throughput is equal to the conversion time plus the acquisition time of the track-and-hold amplifier. For a 2.5 MHz input clock, the maximum throughput is 10 μs.

The operation of tracking and holding is largely transparent to the user. The track-and-hold amplifier switches from track-to-hold mode at the beginning of a conversion.

If a conversion is started using the convst input, a track-and-hold conversion occurs on the rising edge of convst. If cs starts a transition, this transition occurs on the falling edge of cs.

analog input

The three sections differ in the range of analog input voltages they can handle. The AD7870 accepts a ±3 V input signal, the AD7876 accepts a ±10 V input range, and the AD7875 has an input range of 0 V to +5 V.

AD7870 analog input. The analog input range is ±3 V, and the input resistance is typically 15 kΩ. The designed transcoding occurs in the middle between consecutive integer lsb values (i.e. 1/2 lsb, 3/2 lsb, 5/2 lsb). ...fs – 3/2 LSB). The output code is two's complement, 1 lsb=fs/ 4096 =6v/4096=1.46mv. The ideal input/output transfer function is shown in Figure 1.

The AD7876 analog input structure is shown below. The analog input range is ±10 V, and the input resistance is typically 33 kΩ. As before, the designed transcoding occurs in the middle between consecutive integer lsb values. The output code is two's complement, 1 lsb=fs/4096=20v/4096=4.88mv. The ideal input/output transfer function is shown in Figure 1.

Analog input for the AD7875. The input range is 0 V to +5 V, and the input resistance is typically 25 KΩ. Again, the transcoding by design happens in the middle between consecutive integer lsb values. The output code is straight binary with 1 lsb=fs/4096=5v/4096=1.22mv. The ideal input/output transfer function is shown in Figure 2.

Offset and Full Scale Adjustment - AD7870

In most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. With AC coupling, offset errors in the analog domain can be eliminated. The full-scale error effect is linear and should not cause a problem as long as the input signal is within the full dynamic range of the ADC. Some applications require the input signal to span the entire analog input dynamic range. In this application, the offset and full-scale errors must be adjusted to zero.

When adjustment is required, the offset error must be adjusted before the full-scale error. This is accomplished by trimming the offset of the op amp driving the AD7870's analog input when the input voltage is 1/2 lsb below ground. The trimming procedure is as follows: Apply -0.73 mV (-1/2 lsb) at V in Figure 13 and adjust the op amp offset voltage until the ADC output code flashes between 1111 1111 1111 and 0000 0000 0000 0000 . Gain error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure for both cases is as follows (see Figure 3). 1

Positive full scale adjustment

A voltage of 9.9927 V (fs/2−3/2 lsbs) was applied at V. Adjust R2 until the ADC output code flashes between 0111 1111 1110 and 0111 1111 1111 1111.

Negative full scale adjustment

Apply a voltage of −9.9976 V (fs/2 + 1/2 lsb) at V, then adjust R2 until the ADC output code flashes between 1000 0000 0000 and 1000 0000 0001.

Offset and Full Scale Adjustment - AD7875

Positive full scale adjustment

A voltage of 2.9978 V (fs/2−3/2 lsbs) was applied at V. Adjust R2 until the ADC output code flashes between 0111111111 1110 and 0111111 1111.

Negative full scale adjustment

Apply a voltage of -2.9993 V (-fs/2 + 1/2 lsb) at V and adjust R2 until the ADC output code flashes between 1000 0000 0000 and 1000 0000 0001.

Offset and Full Scale Adjustment - AD7876

Similar to the AD7870, offset and full-scale adjustments are not required for most DSP applications using the AD7875. For applications that require adjustment, the offset error must be adjusted before the full-scale (gain) error. This is accomplished by applying an input voltage of 0.61 mV (1/2 lsb) to V in Figure 13 and adjusting the op amp offset voltage until the ADC output code flashes between 0000 0000 and 0000 0000 0001. For full-scale adjustment, apply an input voltage of 4.9982 V (fs-3/2 lsbs) to V and adjust R2 until the ADC output code flashes between 1111 1111 1110 and 1111 1111 1111.

The offset and full-scale adjustments for the AD7876 are similar to the AD7870 just outlined. For those applications that require adjustment, the trimming procedure is as follows: Apply a voltage of -2.44 mV (-1/2 LSB) at V and adjust the op amp offset voltage until the ADC output code is between 1111 1111 1111 and 0000 0000 0000 0000 flashes between. The full-scale error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure for both cases is described in the following sections (see Figure 3).

time and control

The AD7870/AD7875/AD7876 are capable of two basic modes of operation - ING. In the first mode (Mode 1), the convst line is used to initiate the conversion and drive the track and hold it to its hold mode. At the end of the transition, track and hold return to their tracking mode. It is primarily used in digital signal processing and other applications that require accurate sampling in time. In these applications, it is important that the signal samples are sampled at exactly equal intervals to minimize errors due to sampling uncertainty or jitter. For these cases, the convst line is driven by a timer or some precise clock source.

The second mode is achieved by hardwiring the convst line low. This mode (Mode 2) is suitable for systems where the microprocessor fully controls the ADC, including initiating conversions and reading data. The CS initiates the conversion, and the microprocessor usually enters a wait state for the duration of the conversion via busy/int.

Data output format

In addition to these two modes of operation, the AD7870/AD7875/AD7876 offer a choice of three data output formats, one serial and two parallel. The parallel data format is a single, 12-bit parallel word for a 16-bit data bus and a double-byte format for an 8-bit data bus. The data format is controlled by 12/8/CLK input. A logic high on this pin selects only the 12-bit parallel output format. A logic low or -5 V applied to this pin allows the user to access data in serial or byte format. Three pins previously assigned to four msbs in parallel are now used for serial communication, while the fourth pin becomes the control input for byte-formatted data. Three possible data output formats can be selected in either operating mode.

Parallel output format

The two parallel formats provided in this section are a 12-bit wide data word and a two-byte data word. In the first format, all 12-bit data is available simultaneously on db11 (msb) to db0 (lsb). In the second case, two reads are required to access the data. When this data format is selected, the DB11/HBEN pin assumes the HBEN function. HBEN selects which data byte to read from the ADC. When hben is low, the lower 8 bits of data are placed on the data bus during a read operation; when hben is high, the upper 4 bits of a 12-bit word are placed on the data bus. These four bits are right-aligned and thus occupy the lower nibble of data, while the upper nibble contains four zeros.

Serial output format

Serial data is present on the AD7870/AD7875/AD7876 when the 12/8/CLK input is 0 V or -5 V, in which case the DB10/SSTRB, DB9/SCLK and DB8/SData pins assume their serial Function. Serial data is available during conversion with a word length of 16 bits; four leading zeros followed by a 12-bit conversion result starting with msb. Data is synchronized to the serial clock output (SCLK) and is gated by the serial strobe (SSTRB). Data is clocked on a low-to-high transition of the serial clock and is valid on the falling edge of that clock when the sstrb output is low. sstrb goes low three clock cycles after convst and the first serial data bit (the first leading zero) is valid on the first falling edge of sclk. All three serial lines are open-drain outputs and require external pull-up resistors.

The serial clock output comes from the ADC clock source, which can be internal or external. Typically, SCLK is only required during serial transfers. In these cases it can be turned off at the end of the conversion to allow multiple ADCs to share a common serial bus. However, some serial systems (like the tms32020) require a serial clock that runs continuously. Both options can use the 12/8/CLK input on the AD7870/AD7875/AD7876. When this input is at -5 V, the serial clock (SCLK) runs continuously; when 12/8/CLK is at 0 V, SCLK is turned off at the end of the transfer.

Mode 1 interface transitions are initiated by a low pulse on the convst input. The rising edge of this convst pulse starts the conversion and drives the track-and-hold amplifier into its hold mode (AD7870/AD7875/AD7876). The falling edge of the convst pulse starts the conversion, driving the track-and-hold amplifier into hold mode (AD7870A). if CS is low. The busy/int status output assumes its int function in this mode. int is normally high and goes low at the end of the conversion. This int line can be used to interrupt the microprocessor. A read operation on adc accesses the data and resets the int line high on the falling edges of cs and rd. The convst input must be high when cs and rd are low for adc to work properly in this mode. In this mode, the CS or RD input should not be hardwired too low. Data cannot be read from the part during conversion because the onchip latch is disabled during conversion. In applications where accurate sampling is not critical, the convst pulse can be generated by the microprocessor's WR line, or it can be gated with a decoded address. In some applications, the ad7870/ad7875/ad7876 can perform a transition power-up based on the power-on time. In this case, the int line powers up low and requires the AD7870/AD7875/AD7876 to do a dummy read to reset the int line before starting the conversion.

Figure 18 shows the 12-bit parallel mode 1 timing diagram data output format (12/8/CLK=+5 V). A read of the adc at the end of the conversion accesses all 12 bits of data simultaneously. Serial data is not available for this data output format.

Continuous SCLK (dotted line) at 12/8/CLK=-5V;

Discontinuous at 12/8/CLK=0V.

Figure 15. Mode 1 Timing Diagram, Byte or Serial Read shows the Mode 1 timing diagram for bytes and serial data. In Figure 15, int goes low and resets at the end of the conversion, rising by the first falling edge of CS and RD. The first read at the end of the conversion can access the low or high byte of the data, depending on the state of HBEN (for example, Figure 15 shows only the low byte). The figure shows non-continuous and continuous running clocks (dashed lines).

Mode 2 interface

The second interface mode is hardwired, convst low and transitions are initiated by taking cs low when hben is low. The track-and-hold amplifier enters hold mode on the falling edge of cs. In this mode, the /int pin has a busy function. busy goes low at the start of a conversion, remains low during the conversion, and returns high when the conversion is complete. It is typically used in parallel interfaces to drive microprocessors into wait states during conversions. Mode 2 has nothing to do with the AD7870A device.

Figure 16 shows the Mode 2 timing diagram for 12-bit, parallel data output format (12/8/CLK=+5 V). In this case the adc behaves like a slow memory. The main advantage of this interface is that it allows the microprocessor to start converting, wait, and then read the data with a single read instruction. Users don't have to worry about service interruptions or make sure software delays are long enough to avoid reads during transitions.

The Mode 2 timing diagram for bytes and serial data is shown in Figure 17. For double-byte data reads, the low byte (db0–db7) must be accessed first because hben must be low to start conversion. For the first read, the ADC behaves like a slow memory, but the second read accessing the upper byte of the data is a normal read. Serial function operation is the same between Mode 1 and Mode 2. The timing diagram in Figure 17 shows SCLK (dashed line) for discontinuous and continuous operation.

Dynamic Specifications: The AD7870 and AD7875 are specified, 100% tested dynamic performance specifications as well as traditional DC specifications such as integral and differential nonlinearity. Although the AD7876 is not production tested for AC parameters, its dynamic performance is similar to the AD7870 and AD7875. In signal processing applications such as speech recognition, spectrum analysis, and high-speed modems, communication specifications are required. These applications require information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the AD7870 and AD7875 include signal-to-noise ratio, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in detail in the following sections.

Signal-to-noise ratio: snr is the signal-to-noise ratio measured at the ADC output. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding DC, and has a maximum value of half the sampling frequency (fs/2). The signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels, the less quantization noise. The theoretical SNR of a sine wave input is given by SNR=(6.02N+1.76)dB(1), where n is the number of bits. So for an ideal 12-bit converter, SNR = 74dB.

Note that the sine wave signal has very low distortion to the V input sampled at 100 kHz. Quickly generate a Fourier Transform (fft) map at 28, from which signal-to-noise ratio data can be obtained. Figure 18 shows a typical 2048-point FFT plot for the AD7870KN/AD7875KN with an input signal of 25 kHz and a sampling frequency of 100 kHz. The signal-to-noise ratio obtained from this figure is 72.6db. Harmonics should be considered when calculating the signal-to-noise ratio.

significant digits

The signal-to-noise ratio given by Equation 1 is related to the number of bits. Rewriting the formula, as in Equation 2, yields a performance metric expressed in effective bits (n).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio.

Figure 19 shows a typical plot of effective bits versus frequency for the ad7870kn/ad7875kn sampled at 100khz. The number of significant bits is usually between 11.7 and 11.85, corresponding to snr numbers of 72.2 to 73.1db.

Total Harmonic Distortion (THD)

thd is the ratio of the rms sum of the harmonics to the rms value of the fundamental. For the AD7870/AD7875, THD is defined as

where v is the rms amplitude of the fundamental and v, v, v and v are the rms amplitudes of the second to sixth harmonics. The thd is also derived from the fft plot of the adc output spectrum. 123456

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity produces distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3, and many more. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), while third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

Using the CCIF standard, using two input frequencies near the top of the input bandwidth, the second and third order terms have different meanings. The frequency of the second-order term is usually kept at a distance from the original sine wave, while the frequency of the third-order term is usually close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs. In this case, the input consists of two equal amplitude low distortion sine waves. Figure 20 shows a typical IMD plot for the AD7870/AD7875.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for parts of the harmonic buried in the noise floor, the peak is the noise peak.

AC Linear Graph

When a sine wave of a specified frequency is applied to the v input of the ad7870/ad7875 and millions of samples are collected, a histogram showing the frequency of occurrence of each of the 4096 adc codes can be generated. From this histogram data, a linear plot of the ac integral as shown in Figure 21 can be generated. This shows that the AD7870/AD7875 have very good integral linearity performance at an input frequency of 25 kHz. The absence of large peaks in the graph shows good differential linearity. A simplified version of the formula used is outlined below. exist

where:

INL(I) is the integral linear at code i.

V(fs) V(O) is the estimated full scale and offset conversion. v(i) is the estimated transformation of the i code. th v(i) is the estimated transcoding point, which is derived as follows:

where:

INL(I) is the integral linear at code i.

V(fs) V(O) is the estimated full scale and offset conversion. v(i) is the estimated transformation of the i code. th v(i) is the estimated transcoding point, which is derived as follows: