feature

600V-10A three-phase IGBT inverter bridge including control IC for gate drive and protection separate negative DC link terminals for inverter current sensing

application

The single ground power isolation rating of the built-in HVIC is 2500vrms/min.

Very low leakage current due to the use of ceramic substrates

application

Low power AC 100V ~ 253V three-phase inverter drives AC motors to drive home appliance applications such as air conditioners and washing machines

General Instructions

It is an advanced Smart Power Module (SPMTM), a high-performance AC motor drive newly developed and designed by Fairchild, mainly for low-power variable frequency drive applications such as air conditioners and washing machines. It combines optimized circuit protection and drive matching with low-loss IGBTs. System reliability is further enhanced by integrated undervoltage lockout and short circuit protection. The high-speed embedded hvic provides single-supply igbt gate drive capability without optocouplers, further reducing the overall size of the inverter system design.

Separate negative DC terminal.

Integrated power function 600V-10A IGBT inverter for three-phase DC/AC power conversion (see Figure 3)

Integrated drive, protection and system control functions

For inverter high side IGBTs: gate drive circuit, high voltage isolation high speed level shift control circuit undervoltage (UV) protection Note) Figure 10 and Figure 11 give examples of bootstrap circuits that can be used.

For inverter low-side IGBT: gate drive circuit, short-circuit protection (SC) control power circuit under-voltage (UV) protection Fault signal: corresponding to UV fault (low-side source)

Input interface: 3.3/5V CMOS/LSTTL compatible, Schmitt trigger input

Pin configuration

top view

Pin description SPMS protection function time diagram

A1: Control supply voltage rise: After the voltage rises, the circuit starts to work when the next input is applied.

A2: Normal operation: IGBT is on, carrying current.

A3: Under-voltage detection (UVCCD).

A4: The IGBT is turned off regardless of the control input conditions.

A5: The fault output operation starts.

A6: Under-voltage reset (UVCCR).

A7: Normal operation: IGBT on and carrying current.

Figure 6. Undervoltage Protection (Low Voltage Side)

b1: Control power supply voltage rise: After the voltage reaches uvbsr, the circuit starts to work at the next input.

B2: Normal operation: IGBT on and carrying current.

B3: Under Voltage Detection (UVBSD).

B4: No fault output signal although the control input condition is IGBT off.

B5: Brown-out Reset (UVBSR)

Figure 7. Undervoltage Protection (High Side)

(with external shunt resistor and CR connection)

C1: Normal operation: IGBT is on, carrying current.

C2: Short-circuit current detection (SC trigger).

C3: Hard IGBT gate interrupt.

C4: IGBT off.

C5: The fault output timer operation starts: the pulse width of the fault output signal is set by the external capacitor CFO.

C6: Input "L": IGBT off state.

C7: Input "H": IGBT ON state, but during fault output activation, the IGBT does not conduct.

C8: IGBT off state

Figure 8. Short-Circuit Current Protection (Low-Side Operation Only)

Note:

1. The RC coupling (dashed line) of each input may vary depending on the PWM control scheme used in the application and the wiring impedance of the application PCB. The SPM input signal section integrates a 3.3KΩ (typ) pull-down resistor. Therefore, when using external filter resistors, pay attention to the signal voltage drop at the input.

2. Logic inputs are compatible with standard CMOS or LSTTL outputs.

Figure 9. Recommended CPU I/O Interface Circuit These values depend on the pwm control algorithm

Note:

1. It is recommended that the boot diode dbs have soft recovery and fast recovery characteristics.

2. The bootstrap resistor (rbs) should be greater than 3 times re(h). The recommended value for re(h) is 5.6Ω, but it can be increased to 20Ω (max) if the dv/dt is slow

high side.

three. The ceramic capacitor placed between VCC-COM should be above 1UF and mounted as close as possible to the SPM pin.

Figure 10. Recommended Bootstrap Operation Circuit and Parameters

Note:

1. To avoid malfunctions, the wiring at each input should be as short as possible. (less than 2-3cm)

2. By integrating an application-specific Hvic in the SPM, it is possible to couple directly to the CPU terminals without any optocoupler or transformer isolation.

three. The VFO output is an open collector type. This signal line should be pulled up to the positive side of the 5V supply with a resistance of about 4.7KΩ.

4. It is recommended to use csp15 which is about 7 times larger than the bootstrap capacitor cbs.

5. The VFO output pulse width should be determined by connecting an external capacitor (CFOD) between CFOD (pin 7) and COM (pin 2). (Example: If cfod=33nf, then tfo=1.8ms (typical) See Note 5 for calculation method.

6. Input signal is active high type. There is a 3.3KΩ resistor inside the IC to pull each input signal line to GND. When an rc coupling circuit is used, such rc coupling should be set so that the input signal is consistent with the off/on threshold voltage.

7. To prevent errors in the protection function, the wiring around the RF and CSC should be as short as possible.

8. In the short circuit protection circuit, please choose the rfcsc time constant in the range of 1.5~2 microseconds.

9. Each capacitor should be mounted as close as possible to the SPM pin.

10. To prevent surge damage, the wiring between the smoothing capacitor and the P&GND pins should be as short as possible. It is recommended that the capacitor between the P&GND pins be 0.1~0.22uF for high frequency non-inductive.

11. Relays are used in almost all electrical equipment systems of household appliances. In these cases, there should be sufficient distance between the CPU and the relay.

12. CSPC15 should be above 1UF and mounted as close as possible to the SPM pins.