W5500
The W5500 chip is a hardwired TCP/IP embedded Ethernet controller that provides easier connection to embedded systems. The W5500 allows users to have a 10/100 Ethernet MAC and PHY embedded in their applications by using a TCP/IP stack.
Wiznet's hardwired TCP/IP is a market-proven technology that supports TCP, UDP and IPv4, ICMP, ARP, IGMP and PPPoE protocols. The W5500 embeds a 32kbyte internal memory buffer for Ethernet packet processing. If you use the W5500, you can implement ethernet applications just by adding a simple socket program. It's faster and simpler than using other embedded Ethernet solutions. Users can use 8 independent hardware sockets at the same time. SPI (Serial Peripheral Interface) is provided for easy external integration.
single chip microcomputer. The SPI of the W5500 supports 80 MHz speed and new high-efficiency SPI protocol for high-speed network communication. To bring down the system, the W5500 offers WOL (Wake On LAN) and Power Down modes.
feature
- Supports hardwired TCP/IP protocols: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
- Support 8 independent sockets at the same time
- Support power down mode
- Support wake on LAN via udp
- Supports high-speed serial peripheral interface (SPI mode 0, 3)
- Internal 32kbytes memory for send/receive buffers
-Embedded 10BaseT/100BaseTX Ethernet physical layer
- Supports auto-negotiation (full duplex and half duplex, based on 10 and 100)
- Does not support IP fragmentation
-3.3V operation, 5 VI/O signal tolerance
- LED output (full/half duplex, link, speed, active) - 48-pin LQFP lead-free package (7x7mm, 0.5mm pitch)

target application
The W5500 is suitable for the following embedded applications:
- Home network equipment: set-top boxes, PVRs, digital media adapters
- Serial to Ethernet: Access Control, LED Display, Wireless AP Relay, etc.
- Parallel with Ethernet: POS/micro printers, copiers
-USB to Ethernet: storage devices, network printers
- From GPIO to Ethernet: Home Network Sensors
-Security system: DVR, IP camera, kiosk
- Factory and building automation
-Medical monitoring equipment
- Embedded server

A 12.4kΩ (1%) resistor should be connected between the Exres1 pin and analog ground (Agnd) as shown below.

Figure 2. External Reference Resistor

The crystal reference schematic is shown below.

host interface
W5500 provides 4 signals (SCSN, sclk, mosi, miso) for SPI (Serial Peripheral Interface) bus interface for external host interface and operates as spi slave. W5500SPI can be connected to MCU as shown in Figure 4 and Figure 5 according to its operating mode (variable length data/fixed length data mode) which will be explained in chapter 2.3 and chapter 2.4.
In Figure 4, the spi bus can be shared with other spi devices. Because the SPI bus is dedicated to W5500, the SPI bus cannot be shared with other SPI devices.
In variable-length data mode (as shown in Figure 4), the spi bus connected to other spi devices can be shared. However, in fixed-length data mode (Figure 5), the SPI bus is dedicated to the W5500 and cannot be shared with other devices.

The spi protocol defines four modes (mode 0, 1, 2, 3) for its operation.
Varies depending on SCLK polarity and phase. The only difference between SPI mode 0 and spi mode 3 is the polarity of the sclk signal which is inactive.
In SPI modes 0 and 3, data is always latched on the rising edge of SCLK and is always output on the falling edge of SCLK.

W5500 supports SPI Mode 0 and Mode 3. Both mosi and miso signals use a transmission sequence from the most significant bit (msb) to the least significant bit (lsb) for mosi signal transmission and miso signal reception. The mosi and miso signals are always transmitted or received in order from the most significant bit (msb) to the least significant bit (LSB).

SPI operating mode
The W5500 is controlled by an SPI framework (see Chapter 2.2 SPI Framework), which communicates with an external host. W5500 SPI frame contains 3 phases, address phase, control phase and data phase.
The address stage specifies the 16-bit offset address of the W5500 register or TX/RX memory.
The control stage specifies the block to which the offset (set by the address stage) belongs, as well as the read/write access mode and SPI mode of operation (variable-length data/fixed-length data mode).
The data stage specifies random length (n bytes, 1≤n) data or 1-byte, 2-byte and 4-byte data.
If the SPI operating mode is set to Variable Length Data Mode (VDM), the SPI bus signal SCSN must be controlled by an external host with SPI frame stepping.
In variable length data mode, SCSN control start (assert (high to low)) notify w5500 of spi frame start (address phase) and scsn control end (de-assert (low to high)) notify w5500 of spi frame end (random n end of the data phase of the byte).

The W5500 SPI frame consists of a 16-bit offset address in the address phase, an 8-bit control phase and an n-byte data phase as shown in Figure 7.
The 8-bit control phase is reconfigured with block select bits (bsb[4:0]), read/write access mode bits (rwb) and spi mode of operation (om[1:0]).
The block select bits select the block to which the offset address belongs.

W5500 supports sequential data read/write. It processes the data from the database (offset address set for 2/4/n byte order data processing) and the next data by the address stage incrementing the offset address (autoincrement addressing) This address stage specifies the W5500 registers and TX/RX buffer block.
The 16-bit offset address value is transferred sequentially from msb to lsb. The spi frame with 2/4/n bytes data phase supports sequential data read/write, where the offset address is automatically incremented every 1 byte data data phase is controlled by spi operation mode bits om[1:0] setting, data phase Set by two length types, one is n-byte length (VDM mode) and the other type is 1/2/4 bytes (FDM mode).
At this time, 1-byte data is transferred from msb to variable length data mode (VDM) through mosi or miso signal. In VDM mode, the SPI frame data phase length is determined by the external host. This means that the data phase length can have random values (any length from 1 byte to n bytes) according to the scsn control. In VDM mode, OM[1:0] of the control phase should have the value "00".

Figure 8 shows the SPI frame when an external host accesses the W5500 for writing. In VDM mode, in SPI frame control, RWB signal is "1" (write), OM[1:0] is "00" phase. At this point the external host asserts (high to low) the scsn signal and then the host sends all bits of the spi frame to the w5500 via the mosi signal. All bits are synchronized to the falling edge of SCLK. After completing the spi frame transfer, the host deasserts the scsn signal (low to high). Sequential data writes can be supported when SCSN is low and the data phase continues.

In VDM mode, in SPI frame control, RWB signal is "0" (write), OM[1:0] is "00" phase.
At this point, the external host asserts (from high to low) the scsn signal before sending

The host then sends the address and all bits of the control phase to the w5500 signal via mosi. All bits are synchronized to the falling edge of SCLK.
The host then receives all the bits of the data phase and synchronously samples the sclk through the miso signal. After completing the data phase reception, the host deasserts the scsn signal (low to high). Sequence data can support reading when scsn is low and data phases continue to be received.

Fixed Length Data Mode (FDM)
FDM mode can be used when the external host cannot control the SCSN signal. The SCSN signal should be connected low (always to GND), not that the spi bus can be shared with other spi devices. In vdm mode, the data phase length is controlled by scsn. But in FDM mode, the data phase length is controlled by the OM[1:0] value ('01'/'10'/'11').
This is the SPI operation mode bit for the control phase.