General Instructions

, with a redesigned processor core without wasting clocks and memory cycles. So it executes every 8051 instructions faster than the original 8051 at the same crystal speed. Typically, the instruction execution time of the W77L516A is 1.5 to 3 times that of the conventional 8051, depending on the type of instruction. Generally speaking, the overall performance is 2.5 times better than the original at the same crystal speed. At lower clock speeds, the same throughput can increase power consumption. Therefore, the W77L516A is a completely static CMOS design; it can also operate on lower crystal clocks. The W77L516A includes in-system programmable (ISP) 64 kb AP Flash EPROM; 4 kb LD Flash EPROM for program loading; operating voltage from 2.7V to 5.5V; on-chip 1 kb MOVX SRAM; two power saving modes.
2. Features • 8-bit CMOS microcontroller • High-speed architecture at 4 clocks/machine cycle, operating at up to 25 MHz • Pin compatible with standard 80C52 • MCS-51 compatible instruction set • Four 8-bit I/O ports; port 0 has internal pull-up resistors enabled by software An additional 4-bit I/O port and wait state control signal (available on 44-pin PLCC/QFP package)
• Three 16-bit timers • 12 interrupt sources with two priorities • On-chip oscillator and clock circuits • Two enhanced full-duplex serial ports • 64kb system programmable flash EPROM (apflash)
• Loader (ldflash) with 4KB auxiliary flash EPROM
• 256 bytes of temporary memory • 1 kb on-chip SRAM for MOVX instructions
• Programmable watchdog timer • Software reset • Dual 16-bit data pointers • Software programmable access cycles to external RAM/peripherals • Packaging:
- Lead-free (RoHS) DIP 40: W77L516A25DL
- Lead-free (RoHS) PLCC 44: W77L516A25PL
− Lead-free (RoHS) QFP 44: W77L516A25FL
three. pin configuration

5. Function description
The W77L516A is 8052 pin compatible and instruction set compatible. It includes standard 8052 resources such as four 8-bit I/O ports, three 16-bit timer/counters, a full-duplex serial port, and interrupt sources.
W77L516A has faster operation speed and better performance, 8-bit CPU with redesigned core processor without wasting clock and memory cycles. It improves performance not only by running at high frequencies, but also by reducing machine cycles from the standard 8052 cycle of 12 clocks to 4 clock cycles for most instructions. This will increase performance by an average of 1.5 to 3 times. The W77L516A also provides dual data pointers (DPTRS) to speed up block data memory transfers. It also adjusts the duration of MOVX instructions (accessing off-chip data memory) between two machine cycles and nine machine cycles. This flexibility allows the W77L516A to work efficiently with fast and slow RAM and peripherals. Additionally, the W77L516A contains on-chip 1KB MOVX SRAM with addresses between 0000H and 03FFH. It can only be accessed through the MOVX instruction; this on-chip SRAM is optional under software control.
The W77L516A is an 8052 compatible device that provides users with the functionality of the original 8052 device, but with improved speed and power consumption characteristics. It has the same instruction set as the 8051 family, plus one more: DEC DPTR (opcode A5H, DPTR decreases by 1). While the original 8051 series was designed to run for 12 clock cycles per machine cycle, the W77L516A was significantly slower, running only 4 clock cycles per machine cycle. This naturally speeds up the execution of instructions. So compared to the original 8052, the W77L516A can run at higher speeds, even with the same crystal. Since the W77L516A is a fully static CMOS design, it can also run at a lower crystal clock, providing the same throughput in terms of instruction execution while reducing power consumption.
The 4 clocks per machine cycle feature in the W77L516A is responsible for three times the execution speed. The W77L516A has all the standard features of the 8052 with some additional peripherals and features.
Input and output ports
The W77L516A has four 8-bit ports and an additional 4-bit port. Port 0 can be used as an address/data bus when an external program is running or when MOVC or MOVX instructions access external memory/devices. In these cases, it has a strong pull-up and pull-down that doesn't require any external pull-up. Otherwise, it can be used as a general-purpose I/O port with open-drain circuitry. When port 0 is used as the address/data bus, port 2 is mainly used as the upper 8 bits of the address bus. It also has strong pull-up and pull-down functions when it acts as an address bus. Ports 1 and 3 function as I/O ports with alternate functions. Port 4 is only available on the 44-pin PLCC/QFP package type. it is a general purpose
The I/O ports act as port 1 and port 3. P4.0 has an alternate function cp rl/2 which is a wait state control signal. When the wait state control signal is enabled, only P4.0 is input.
Serial input and output
The W77L516A has two enhanced serial ports that function similarly to the serial ports of the original 8052 series. However, the serial port on the W77L516A can also work in a different mode for timing similarity. Note that serial port 0 can use either timer 1 or 2 as a baud rate generator, but serial port 1 can only use timer 1 as a baud rate generator. The serial port has enhancements for automatic address recognition and framing error detection.
timer
The W77L516A has three 16-bit timers that function similarly to the 8052 series timers. When used as a timer, it can be set to run 4 clocks or 12 clocks per count, giving the user the option to run in a timing mode that emulates the original 8052. The W77L516A has an additional function, the watchdog timer. This timer is used as a system monitor or a very long period timer.
interrupt
The interrupt structure of the W77L516A is slightly different from the standard 8052. The number of interrupt sources and vectors has increased due to the presence of additional features and peripherals. W77L516A provides 12 interrupt resources with two priority levels, including 6 external interrupt sources, timer interrupt, serial I/O interrupt.
Data pointer The original 8052 has only one 16-bit data pointer (dpl, dph). In the W77L516A, there is an additional 16-bit data pointer (DPL1, DPH1). This new data pointer uses two SFR locations that were not used in the original 8052. In addition, there is an additional instruction DEC DPTR (operation code A5H), which helps to increase the user's programming flexibility.
Power Management Like the standard 80C52, the W77L516A also features idle and power-down modes of operation. The W77L516A offers a new economy mode that allows the user to divide the internal clock rate by 4, 64 or 1024 . In idle mode, the clock to the CPU core is stopped, while the timers, serial ports and interrupt clocks continue to work. In power-down mode, all clocks are stopped and chip operation is completely stopped. This is the lowest power state.
On-chip data SRAM
The W77L516A has 1K bytes of data space SRAM that can be read/written and is memory mapped. The on-chip MOVX SRAM is implemented by the MOVX instruction. It is not used for executable program memory. There is no conflict or overlap between the 256 bytes of scratchpad RAM and the 1K bytes of MOVX SRAM because they use different addressing modes and separate instructions. On-chip MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After reset, the DME0 bit is cleared so that the on-chip MOVX SRAM is disabled and all data memory spaces 0000h−ffffh access external memory.
6. memory organization
The W77L516A divides the memory into two separate parts, program memory and data memory. Program memory is used to store instruction opcodes, while data memory is used to store data or store mapped devices.
Program Memory Program memory on the standard 8052 can only be addressed up to 64 kilobytes long. All instructions are fetched and executed from this memory area. MOVC instructions can also access this memory area. In System Programming (ISP) there is an auxiliary 4KB flash EPROM bank (ldflash) that resides the user loader. apflash allows serial or parallel download according to the user loader in ldflash.
data storage
The W77L516A can access up to 64kbytes of external data memory. MOVX instructions can access this memory area. Unlike the 8051 series, the W77L516A contains on-chip 1K bytes of MOVX SRAM for data memory, which can only be accessed by MOVX instructions. These 1K bytes of SRAM are between addresses 0000H and 03FFH. Under software control, access to the on-chip MOVX SRAM is optional. When enabled by software, any MOVX instruction that uses this area will go to on-chip RAM. MOVX addresses greater than 03ffh automatically go to external memory via ports 0 and 2. When disabled, the 1KB memory region is transparent to the system memory map. Any MOVX pointing to the space between 0000H and FFFFH will go to the expansion bus on ports 0 and 2. This is the default condition. Additionally, the W77L516A has standard 256 bytes of on-chip scratchpad RAM. This can be accessed by direct or indirect addressing. There are also some Special Function Registers (SFRs), which can only be accessed through direct addressing. Because the scratch line RAM is only 256 bytes, it can only be used when the data content is small. If there is a large data content, two options are available. One is the on-chip MOVX SRAM and the other is external data memory. The on-chip MOVX SRAM can only be accessed by MOVX instructions, the same as external data memory. However, on-chip RAM has the fastest access time.

special function register
The W77L516A uses Special Function Registers (SFRs) to control and monitor peripherals and their modes.
The SFR is located in register location 80 ffh and is only accessed by direct addressing. Some SFRs are bit addressable. This is useful if one wishes to modify specific bits without changing other bits. A bit-addressable SFR is an SFR whose address ends with 0 or 8. The W77L516A contains all the SFRs in the standard 8052. However, some additional SFRs are added. In some cases, unused bits in the original 8052 were given new functions. The list of SFRs is as follows. The table is compressed at eight locations per row. Empty locations indicate that these addresses have no registers. When a bit or register is not implemented, it will read high.

command timing
The instruction timing of the W77L516A is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Additionally, it provides users with an insight into the timing difference between the W77L516A and the standard 8032. In the W77L516A, each machine cycle is four clock cycles long. Each clock cycle is designated as a state. Thus, each machine cycle consists of four states, C1, C2, C3, and C4 in that order. Since the execution time of each instruction is shortened, both clock edges are used for internal timing. Therefore, it is important that the duty cycle of the clock should be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the W77L516A performs an opcode fetch per machine cycle. Therefore, in most instructions, the number of machine cycles required to execute the instruction is equal to the number of bytes in the instruction. Of the 256 available opcodes, 128 are single-cycle instructions. Therefore, more than half of the opcodes in the W77L516A are executed in only four clock cycles. Most of the two cycle instructions are instructions with a two byte instruction code. However, some instructions are only one byte instructions, but they are two loop instructions. The most important instruction is the movx instruction. In the standard 8032, MOVX instructions are always two machine cycles long. However, in the W77L516A, the user has a description of the function to extend this duration from 2 machine cycles to 9 machine cycles. The RD and WR strobe lines are also extended proportionally. This gives users the flexibility to access fast and slow peripherals with no external circuitry and minimal software overhead. The remaining instructions are three, four or five machine loop instructions. Note that in the W77L516A there are five different types depending on the number of machine cycles, whereas in the standard 8032 there are only three. However, in the W77L516A, each machine cycle consists of only 4 clock cycles compared to the standard 8032's 12 clock cycles. So even with the increased number of classes, clock cycles per instruction are at least 1.5 to 3 times faster than the standard 8032

MOVX instruction
The W77L516A, like the standard 8032, uses MOVX instructions to access external data memory. The data memory includes off-chip memory and memory-mapped peripherals. While the result of the movx instruction is the same as in the standard 8032, the operation and timing of the strobe signal has been modified to give the user more flexibility.
There are two types of movx instructions, movx@ri and movx@dptr. In movx@ri, the addresses of external data come from two sources. The lower 8 bits of the address are stored in the RI register of the selected working register bank. The upper 8 bits of the address come from the Port 2 SFR. In the movx@dptr type, the full 16-bit address is provided by the data pointer.
Since the W77L516A has two data pointers, dptr and dptr1, the user must choose between these two pointers by setting or clearing the dps bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR and is present at position 86H. No other bits in this SFR have any effect, and they are set to 0. When dps is 0, dptr is selected; when it is set to 1, dptr1 is selected. The user can switch between DPTR and DPTR1 by toggling the DPS bit. The fastest way is to use the inc instruction. The advantage of having two data pointers is most apparent when performing block move operations. The accompanying code shows how to use two separate data pointers to speed up the execution time of code that performs the same task.

In the instruction, W77L516A provides another hardware signal wait to achieve longer external data access time. This wait state control signal is an alternate function of P4.0, so only the 44-pin PLCC/QFP packet type can be called. The wait state control signal can be enabled by setting the ws (wscon.7) bit. When enabled, the setting of the stretch value determines
The minimum length of a MOVX instruction cycle during which the device will sample the wait pin for each C3 state before the rising edge of the read/write strobe. Once the signal is recognized, one more machine cycle (wait state cycle) is inserted in the next cycle. Inserted wait state cycles are unlimited, so a MOVX instruction cycle will end with the wait state control signal deactivated. Use wait state control signals to allow dynamic access to timing of selected external peripherals. The WS bit is accessed by the timed access protection process.
Set the ws bit and stretch value = 0 to enable wait signals.
power management
The W77L516A has several features that help users control the power consumption of the device. The power saving functions basically have power down mode, economy mode and idle running mode.
Idle Mode The user can place the device in idle mode by writing a 1 to bit pcon.0. The instruction that sets the idle bit is the last instruction that will be executed before the device enters idle mode. In idle mode, the CPU's clock is suspended instead of interrupts, timers, watchdog timers, and serial port blocks. This will force the CPU state to freeze; the program counter, stack pointer, program status word, accumulator and other registers save their contents. The ALE and PSEN pins are held high in the idle state. The port number holds the logical state when idle is active. Idle mode can be terminated in two ways. Since the interrupt controller is still active, activating any enabled interrupt can wake up the processor. This will automatically clear idle bits, terminate idle mode, and execute the Interrupt Service Routine (ISR). After the ISR, program execution will continue from the instruction that put the device into idle mode.
Idle mode can also be exited by activating a reset. The device can be reset by applying a high level on the external RST pin, a power-on reset condition, or a watchdog timer reset. The external reset pin must be held high for at least two machine cycles, or 8 clock cycles, to be recognized as a valid reset. In reset condition, the program counter is reset to 0000H and all SFRs are set to reset condition. Because the clock is already running, there is no delay and execution starts immediately. In idle mode, the watchdog timer continues to run, and if enabled, a timeout will cause a watchdog timer interrupt, which will wake up the device. Software must reset the watchdog timer in order to preempt the reset that occurs after 512 clock cycles. When the W77L516A exits from idle mode by reset, the instruction to put the device into idle mode is not executed. So there is no danger of accidental writes.
The power consumption of an eco-mode microcontroller is related to the operating frequency. The W77L516A offers an economy mode that dynamically reduces the internal clock rate without external components. By default, one machine cycle takes 4 clocks. In economy mode, software can select 4, 64 or 1024 clocks per machine cycle. It keeps the CPU running at an acceptable speed but eliminates power consumption. In idle mode, clocks to the core logic are stopped, but all clocked peripherals (such as watchdog timers) still run at the rate of clock/4. In economy mode, all clock peripherals run at the same speed as the core logic. Therefore, Eco mode provides lower power consumption than Idle mode.

The instruction rate selection will take effect after a one instruction cycle delay. Switching to divide by 64 or 1024 mode must first go from divide by 4 mode. This means that software cannot switch directly between clock/64 and clock/1024 modes. The CPU must first go back to clock/4 mode and then go to clock/64 or clock/1024 mode.
In economy mode, the serial port cannot receive/transmit data correctly due to baud rate changes. In some systems, external interrupts may require the fastest process, limiting the slowdown in operation. To address these challenges, the W77L516A provides a toggle function that allows the CPU to return to clock/4 mode immediately upon serial operation or when an external interrupt is triggered. The toggle function is enabled by setting the SWB bit (PMR.5). A serial port receive/transmit or qualified external interrupt, enabled and acknowledged without a blocking condition, will cause the CPU to return to divide-by-4 mode. For serial port reception, if serial port reception is enabled, the toggle is generated by the falling edge associated with the start bit. When the serial port transmits, an instruction to write a byte of data to the serial port buffer will cause a toggle to ensure proper transmission. The failback function is not affected by the serial port interrupt flag. After a switch is generated, software can manually return the CPU to economy mode. Note that when toggle is enabled, modifications to clock control bits CD0 and CD1 are ignored during serial port transmit/receive. A watchdog timer reset, power-on/fault reset, or external reset will force the CPU to return to divide-by-4 mode.
Power-Down Mode The device can enter Power-Down mode by writing a 1 to bit PCON. The instruction to do this will be the last instruction to execute before the device enters shutdown mode. In power-down mode, all clocks are stopped and the device is stopped. All activity ceases completely and power consumption is reduced to the lowest possible value. Ale and PSEN sales were pulled lower in this state. The port pins output the values held by their respective SFRs.
The W77L516A will exit power-down mode by reset or by enabling an external interrupt pin that is level-detected. An external reset can be used to exit a power-down state. A high level on the RST pin terminates power-down mode and restarts the clock. Program execution will resume at 0000h. In shutdown mode, the clock is stopped, so the watchdog timer cannot provide a reset to exit shutdown mode.
The W77L516A can wake-up from power-down mode by forcing activation of an external interrupt pin, provided the corresponding interrupt is enabled, the global enable (EA) bit is set and the external input is set to level detect mode. If these conditions are met, a low level on the external pin restarts the oscillator. The device then executes the interrupt service routine for the corresponding external interrupt. After the interrupt service routine completes, program execution returns to the instruction after placing the device in shutdown mode, and then continues execution.

Externally reset the device to continuously sample the first pin in the C4 state of each machine cycle. Therefore, the RST pin must be held for at least 2 machine cycles to ensure that a valid RST high is detected. The reset circuit then applies the internal reset signal synchronously. Therefore, reset is a synchronous operation and requires a running clock for external reset.
Once the device is in reset, it will remain unchanged as long as RST is 1. Even after RST is deactivated, the device will remain in reset for up to two machine cycles before executing the program from 0000H. There are no flags associated with external reset conditions. However, since the other two reset sources have flags, an external reset can be considered a default reset if these two flags are cleared.
Software must clear the por flag after reading or it will not be able to correctly determine the source of future resets. In the event of a power failure, i.e. below VRST, the device will go into reset again. When power returns to normal operating levels, the device will again perform the power-on reset delay and set the POR flag.
Watchdog Timer Reset The Watchdog Timer is a free-running timer with a programmable time-out interval. The user can clear the watchdog timer at any time to start counting again. When the timeout interval is reached, the interrupt flag will be set. If the watchdog reset is enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog timer will generate a reset. This will put the device into a reset state. The reset condition is maintained by hardware for two machine cycles. Once the reset is removed, the device will start executing from 0000H.
Most SFRs and registers on a reset state device will go to the same state in reset state. The program counter is forced to 0000h and remains there as long as the reset condition is applied. However, the reset state does not affect the on-chip RAM. During the reset process, the data in RAM will be saved. However, the stack pointer is reset to 07h, so the stack contents are lost. If VDD falls below about 2V, RAM contents will be lost, as this is the minimum voltage level required for RAM to function properly. Therefore, after the first power-on reset, the RAM contents will be indeterminate. In the event of a power failure, if the power supply falls below 2V, the RAM contents will be lost.
After reset, most SFRs are cleared. Interrupts and timers are disabled. If the reset source is a por, the watchdog timer will be disabled. The port SFR is written with FFH, making the port pin high. Port 0 is floating because it has no on-chip pull-offs and ongoing instructions. If the external interrupt is int0 to int5, it is sampled at c3 every machine cycle and its corresponding interrupt flag iex is set or reset. The timer 0 and 1 overflow flags are set at c3 of the machine cycle where the overflow occurred. These flag values are only polled on the next machine cycle. If a request is active and all three conditions are met, the hardware-generated lcall is executed. This lcall itself requires four machine cycles to complete. Therefore, there are at least five machine cycles between setting the interrupt flag and executing the interrupt service routine.
If any of these three conditions are not met, longer response times should be expected. If the priority of the service is higher or equal, then the interrupt latency obviously depends on the nature of the currently executing service routine. Additional latency is introduced if the polling cycle is not the last machine cycle of the instruction being executed. If the W77L516A is performing a write to IE, IP, EIE or EIP followed by a MUL or DIV instruction, the maximum response time will occur (if no other interrupts are in service). The longest response time is 12 machine cycles from the activation of the interrupt source. This includes 1 machine cycle to detect the interrupt, 2 machine cycle to complete IE, IP, EIE or EIP access, 5 machine cycle to complete the MUL or DIV instruction, 4 machine cycle to complete the hardware LCall to the interrupt vector location.
Therefore, in a single interrupt system, the interrupt response time is always more than 5 machine cycles, not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock cycles. Note that in the standard 8051, the maximum latency is 8 machine cycles, which equates to 96 machine cycles. In terms of clock cycles, this is a 50% reduction.
Programmable Timer/Counter
The W77L516A has three 16-bit programmable timers/counters and a programmable watchdog timer. The watchdog timer is distinct in operation from the other two timers.
Timer/Counter 0 and 1
The W77L516A has two 16-bit timer/counters. Each timer/counter has two 8-bit registers, forming a 16-bit count register. For timer/counter 0, they are th0, upper 8-bit register and tl0, lower 8-bit register. Likewise, Timer/Counter 1 has two 8-bit registers, th1 and tl1. These two can be configured as timers, counting machine cycles, or as counters to count external inputs.
When configured as "timer", the timer counts clock cycles. The timer clock can be programmed to be 1/12 of the system clock or 1/4 of the system clock. In "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in the case of timer 0 and t1 in the case of timer 1. On each machine cycle of C4, the T0 and T1 inputs are sampled. If the sampled value is high in one machine cycle and low in the next machine cycle, a valid high-low transition on the pin is recognized and the count register is incremented. Since two machine cycles are required to identify a negative transition on a pin, the maximum rate at which counting can be done is 1/24 of the master clock frequency. In "timer" or "counter" mode, the count register will be updated at c3. Therefore, in "timer" mode, discernible negative transitions on pins t0 and T1 can cause the count register value to be updated only on machine cycles where a negative edge is detected.
The "timer" or "counter" function is selected by the "C/T" bits in the TMOD special function register. Each timer/counter has a select bit, bit 2 of TMOD selects the function of timer/counter 0, and bit 6 of TMOD selects the function of timer/counter 1. Additionally, each timer/counter can be set to operate in any of four possible modes. Mode selection is done by the m0 and m1 bits in the TMOD SFR.
Time base selection
The W77L516A provides users with two timer operation modes. The timer can be programmed to work like a standard 8051 series, counting at 1/12 the clock speed. This will ensure that the timing loops on the W77L516A and the standard 8051 can match. This is the default operating mode of the W77L516A timer. The user can also choose to count in turbo mode and the timer will increment at 1/4 clock speed. This will immediately triple the count speed. This selection is done by the T0M and T1M bits in the CKCON SFR. A reset sets these bits to 0 and the timer then operates in standard 8051 mode. The user should set these bits to 1 if the timer is to operate in turbo mode.
Mode 0
In Mode 0, the timer/counter acts as an 8-bit counter, 5 bits, divided by 32 prescales. In this mode, we have a 13-bit timer/counter. The 13-bit counter consists of 8 bits of THX and 5 low-order bits of TLX. The upper 3 bits of TLX are ignored.
The negative edge of the clock increases the count in the TLX register. When the fifth bit in TLX moves from 1 to 0, the count in the THX register is incremented. When the count in thx moves from ffh to 00h, the overflow flag tfx in tcon sfr is set. Only if TRX is set to gate=0 or intx=1. When C/T is set to 0, it will count clock cycles,
If c/t is set to 1, the transition count on timer 0's t0 (p3.4) is 1 to 0, and the transition count on timer 1's t1 (p3.5) is 1 to 0. When the 13-bit count reaches 1ffh, the next count will roll it to 0000h. Sets the timer overflow flag tfx of the associated timer, if enabled, an interrupt will occur. Note that when used as a timer, the time base can be clock cycles/12 or clock cycles/4, selected by bit txm of the CKCON SFR.

Mode 1
Mode 1 is similar to Mode 0, except that the count register forms a 16-bit counter instead of a 13-bit counter. This means that all bits of THX and TLX are used. The rollover occurs when the timer moves from the ffffh count to 0000h. The timer overflow flag tfx for the associated timer is set and if enabled, an interrupt will occur. The time base selection in timer mode is similar to the time base selection in Mode 0. The operation of the gate function is similar to that in mode 0.
Mode 2
In mode 2, the timer/counter is in auto-reload mode. In this mode, TLX acts as an 8-bit count register, while THX holds the reload value. When the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the contents of thx, and the counting process continues from here. The reload operation leaves the contents of the THX register unchanged. Counting is enabled by the TRX bit and properly setting the gate and intx pins. Like the other two modes, 0 and 1 Mode 2 allows counting clock cycles (clock/12 or clock/4) or pulses on pin tn.

Mode 3
Mode 3 has different methods of operation for the two timers/counters. For timer/counter 1, mode 3 freezes the counter only. However, Timer/Counter 0 configures TL0 and TH0 as two separate 8-bit count registers. The logic of this mode is shown in the figure. TL0 uses timer/counter 0
Control bits c/t, gate, tr0, int0, and tf0. TL0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin t0 as determined by C/T (tmod.2). TH0 is forced to act as a clock cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from timer/counter 1. Mode 3 is used when an additional 8-bit timer is required. While Timer 0 is used in Mode 3, Timer 1 can still be used in Modes 0, 1, and 2, but with limited flexibility. While its basic functionality is maintained, it no longer controls its overflow flag tf1 and enable bit tr1. Timer 1 can still be used as a timer/counter, and the gate and int1 pins are reserved. In this case, it can be turned on and off by switching it from Mode 3 to its own Mode 3. It can also be used as a baud rate generator for the serial port.
Timer/Counter 2
Timer/Counter 2 is a 16-bit up/down counter configured by the t2mod register and controlled by the t2con register. Timer/Counter 2 has capture/reload capability. As with the Timer 0 and Timer 1 counters, there is considerable flexibility in selecting and controlling the clock and defining the mode of operation. The clock source for Timer/Counter 2 can be selected from the external t2 pin (c/t2=1) or the crystal oscillator, which is divided by 12 or 4 (c/t2=0). Then, the clock is enabled when tr2 is 1 and disabled when tr2 is 0.

Capture Mode Capture mode is enabled by setting the cp rl/2 bit in the t2con register to 1. In capture mode, Timer/Counter 2 operates as a 16-bit up-counter. When the counter rolls over from ffffh to 0000h, an s2 bit will be set, which will generate an interrupt request. If the exen2 bit is set, then a negative transition of the t2ex pin will cause the values in the tl2 and th2 registers to be captured by the rcap2l and rcap2h registers. This operation will also set the exf2 bit in t2con, which will also generate an interrupt. Setting the t2cr bit (t2mod.3), the W77L516A allows hardware to automatically reset Timer 2 after capturing the values of tl2 and th2.
auto-reload mode, counting

Auto-reload mode as an up-counter can be enabled by clearing the cp rl/2 bit in the t2con register and clearing the dcen bit in the t2mod register. In this mode, Timer/Counter 2 is a 16-bit up-counter. When the counter rolls over from ffffh, a reload is generated that reloads the contents of the rcap2l and rcap2h registers into the tl2 and th2 registers. The reload operation also sets the s2 bit. A negative transition of the t2ex pin will also cause a reload if the exen2 bit is set. This operation also sets the exf2 bit in t2con.
Auto reload mode, count up/down

If the cp rl/2 bit in t2con is cleared and the dcen bit in t2mod is set, timer/counter 2 will be in auto-reload mode as an up/down counter. In this mode, Timer/Counter 2 is an up/down counter whose direction is controlled by the T2EX pin. A 1 on this pin makes the counter count. Overflow while counting will cause the counter to be reloaded with the contents of the capture register. The next count down with the contents of the timer/counter equal to the capture register will load a ffff in timer/counter 2. In both cases, a reload will set this bit. Reloading also toggles the exf2 bit. However, in this mode, the exf2 bit cannot generate interrupts.
Baud Rate Generator Mode The baud rate generator mode is enabled by setting the rclk or tclk bits in the t2con register. In baud rate generator mode, timer/counter 2 is a 16-bit counter that automatically reloads when the count rolls over from ffffh. However, scrolling does not set the TF2 bit. If the exen2 bit is set, a negative transition of the t2ex pin will set the exf2 bit in the t2con register and cause an interrupt request.
Programmable clock output

Timer 2 is equipped with a new off-duty punch-in function, which outputs a 50% duty cycle clock on P1.0. It can be called as a programmable clock generator. To configure Timer 2 for clock output mode, software must start it by setting bits t2oe=1, c/t2=0 and cp/rl=0. Setting bit TR2 will start the timer. This mode is similar to the baud rate generator mode, it does not generate an interrupt on Timer 2 overflow. So Timer 2 can be used as baud rate generator and clock generator at the same time. The clock output frequency is determined by the following formula:
clock output frequency = oscillator frequency / [4 x (65536-RCAP2H, RCAP2L)]
watchdog timer

The watchdog timer is a free-running timer that can be programmed by the user as a system monitor, time base generator, or event timer. It's basically a set of dividers that divide the system clock. The divider output is optional and determines the timeout interval. When a timeout occurs, a flag is set, which causes an interrupt if enabled, and a system reset if enabled. Interrupts will occur if individual interrupt enable and global enable are set. The interrupt and reset functions are independent of each other and can be used individually or together according to user software.
The watchdog timer should first be restarted using the RWT. This ensures that the timer starts from a known state. The RWT bit is used to restart the watchdog timer. This bit is auto-clear, that is, after writing a 1 to this bit, the software will automatically clear the bit. The watchdog timer will now count clock cycles. The timeout interval is selected by two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the selected timeout occurs, the Watchdog Interrupt Flag WDIF (WDCON.3) will be set. After the timeout occurs, the watchdog timer waits an additional 512 clock cycles. If the watchdog reset EWT (WDCON.1) is enabled, then 512 clocks after the timeout, without the RWT, a system reset due to the watchdog timer will occur. This will last for two machine cycles and will set the watchdog timer reset flag wtrf (wdcon.2). This indicates to the software that the watchdog is the cause of the reset.
When used as a simple timer, reset and interrupt functions are disabled. The timer will set the WDIF flag whenever the timer completes the selected interval. The WDIF flag is polled to detect a timeout, and the RWT allows software to restart the timer. The watchdog timer can also be used as a very long timer. In this case, the interrupt function is enabled. Every time a timeout occurs, an interrupt will occur if the global interrupt enable EA is set.
The main purpose of the watchdog timer is as a system monitor. This is important in real-time control applications. Under certain power failure or electromagnetic interference conditions, the processor may start executing erroneous code. If not checked, the whole system may crash. Using the watchdog timer interrupt during software development will allow the user to select the ideal watchdog reset location. The code is first written without a watchdog interrupt or reset. Then, the watchdog interrupt is enabled to identify the code location where the interrupt occurred. Users can now insert instructions to reset the watchdog timer, which will allow code to run without any watchdog timer.
interrupt. Now that the watchdog timer reset is enabled, the watchdog interrupt may be disabled. If any error code is executed now, the reset watchdog timer instruction will not execute at the desired instant and a watchdog reset will occur. The watchdog timeout selection will result in different timeout values depending on the clock speed. When enabled, the reset will occur 512 clocks after the timeout occurs.

Serial port
The serial port in the W77L516A is a full-duplex port. The W77L516A provides users with additional functions such as framing error detection and automatic address recognition. Serial ports are capable of synchronous and asynchronous communication. In synchronous mode, the W77L516A generates the clock and operates in half-duplex mode. In asynchronous mode, full-duplex operation is possible. This means it can send and receive data at the same time. Both transmit registers and receive buffers are programmed as SBUF special function registers. However, any writes to sbuf will be sent to the transmit register, while reads from sbuf will be to the receive buffer register. The serial port can work in four different modes as follows.
Mode 0

This mode provides synchronous communication with external devices. In this mode, serial data is transmitted and received on the RxD line. TXD is used to transmit the shift clock. The TxD clock is provided by the W77L516A, whether the device is transmitting or receiving. Therefore, this mode is a half-duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is sent/received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. The baud rate is determined by the sm2 bit (scon.5). When this bit is set to 0, the serial port runs at 1/12 the clock. When set to 1, the serial port runs at 1/4 of the clock. The addition of programmable baud rate in Mode 0 is the only difference between the standard 8051 and the W77L516A.
The functional block diagram is shown below. Data goes in and out of the serial port on the RxD line. The TXD line is used to output the shift clock. The shift clock is used to shift data in and out of the W77L516A and the device on the other end of the line. Any instruction that results in a write to sbuf will initiate a transfer. The shift clock will be activated and the data will be shifted out on the RxD pin until all 8 bits have been transferred. If sm2=1, the data on rxd will appear 1 clock cycle before the falling edge of the shift clock on txd. Then the clock on txd stays low for two clock cycles and then goes high again. If sm2=0, the data on rxd will appear 3 clock cycles before the falling edge of the shift clock on txd. Then the clock on txd stays low for 6 clock cycles and then goes high again. This ensures that on the receiver side, the data on the RxD line can be clocked on the rising edge of the shift clock on TXD or locked when the TXD clock is low