Features In-system programmable 3.3V proms
Xilinx FPGA Configuration
20,000 program/erase cycle endurance Program/erase over full industrial voltage and temperature range (–40°C to +85°C)
IEEE Std 1149.1 boundary scan (JTAG) support
JTAG command initiates standard FPGA configuration Simple interface with FPGA Cascaded storage of long or multiple bit streams Low power Advanced CMOS flash processing
Parallel (up to 264 MB/s at 33 MHz)
5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V signals
3.3V or 2.5V output capability Design support using Xilinx ISE Fundamentals software package Available in PC20 , SO20, PC44 and VQ44 packages Pb-free (Pb-free) package description

Xilinx introduced the XC18V00 family of in-system programmable configuration proms (Figure 1). This 3.3V family of devices includes a 4Mbit, a 2Mbit, a 1Mbit and a 512Kbit programmable read-only memory-
A low-cost method for reprogramming and storing XilinxFPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a configuration clock that drives the programmable read-only memory. very short passage
Data is available on the programmable ROM data (D0) pin connected to the FPGA DIN for a period of time after CE and OE are enabled.
pin. New data is available on the rising clock edge within a short access time after each access. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in slave serial mode, the PROM and PGA are clocked by an external clock.
X-Ref Target When the FPGA is in master select map mode, the FPGA generates a configuration clock that drives the programmable read-only memory. When the FPGA is in Slave Parallel or Slave Select Mapping mode, an external oscillator generates a configuration clock that drives the PROM and FPGA. Data is available on the PROM data (D0-D7) pins when CE and OE are enabled. New data is available within a short access time after each rising clock edge. Data is clocked into the FPGA on subsequent rising edges of CCLK. The free-running oscillator can be used in slave parallel or slave SELECMAP mode.
By using the ceo output it is possible to cascade multiple devices to drive the CE input of the following devices. The clock inputs and data outputs of all proms in the chain are interconnected. All devices are compatible and can be used with other members of the family or
The xC17v00 one-time programmable serial programmable read-only memory family.

pinout diagram

In system programming, the programmable PROMs in the system can be programmed individually, or two or more PROMs can be linked together and programmed in the system through the standard 4-pin JTAG protocol, as shown in Figure 2. Provides fast and efficient design iteration in system programming and eliminates unnecessary packet processing or device socketing. Xilinx development systems provide programming data sequences using Xilinx shock software and download cables, third-party JTAG development systems, JTAG-compatible board testers, or simple microprocessor interfaces that emulate JTAG instruction sequences. The shock software also outputs Serial Vector Format (SVF) files for use with any tool and automated test equipment that accepts the SVF format.
During system programming, all outputs are held in the high-Z state or at the clamp level.
Photoelectric reset
The ISP programming algorithm requires that a reset be issued to bring OE low.
external programming
Xilinx reprogrammable proms can also be programmed by third-party device programmers, providing the additional flexibility of using pre-programmed devices with in. -
X-Ref target system programmable options for future enhancements and design changes.
Reliability and Durability
Xilinx in-system programmable products offer a guaranteed endurance level of 20,000 during system program/erase cycles and retain data for at least 20 years. Each device meets all functional, performance and data retention specifications within this endurance limit. For equipment quality, reliability, and process node information, see ug116, Xilinx Equipment Reliability Report.
security by design
The Xilinx in-system P/P ROM devices include advanced data security features to fully protect programming data from unauthorized reading via JTAG. Table 3 shows the available security settings.
The user can set the read security bit to prevent the internal programming mode from being read or copied via JTAG. Once set, it allows device wipe. Wiping the entire device is the only way to reset the read security bit.

IEEE 1149.1 Boundary Scan (JTAG)
The XC18V00 series is fully compliant with IEEE Standard 1149.1 Boundary Scan, also known as JTAG. Test Access Ports (TAPs) and registers are provided to support all required boundary scan instructions, as well as many optional instructions specified by IEEE Standard 1149.1. Additionally, a JTAG interface is used to implement in-system programming (ISP) to facilitate configure, erase and verify operations on the XC18V00 device.

Instruction Register Values Loaded into IR as part of an instruction scan sequence Boundary Scan Registers Boundary Scan Registers are used to control and observe the state of device pins during extest, sample/preload, and clamp instructions. Each output pin on the XC18V00 has two register stages that act on boundary scan registers, while each input pin has only one register stage.
For each output pin, the register stage closest to TDI controls and observes the output state, while the second stage closest to TDO controls and observes the pin's high-Z enable state.
For each input pin, the register level controls and observes the input state of the pin.
identification register

An IDcode is a fixed, vendor-specified value that electronically identifies the manufacturer and type of device to be handled. The width of the IDcode register is 32 bits. The idcode register can be shifted out for inspection using the idcode instruction. IDcode can be provided to any other system component via JTAG.
See Table 5 for xc18v00 idcode values.

The IDcode register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1, where
V=Mold version number F=Series code (XC18V00 series is 50H) A=ISP PROM product ID (XC18V04 is 26H or 36H ) C=Company code (Xilinx is 49H)
Note: The LSB of the IDcode register is always read as a logic "1" as defined by IEEE Standard 1149.1.

notes:
1. in the idcode field Represents the revision code (hex) of the device, which may vary.
User code instructions allow access to a 32-bit user-programmable scratchpad that is typically used to provide information about what to program the device. User programmable identification codes can be removed for inspection by using user code instructions. This code is loaded into the user code register during programming of the XC18V00 device. If the device is empty or not loaded during programming, the user code register contains ffffffffh.
XC18V00 Tap Features

The XC18V00 series performs in-system programming and IEEE1149.1 boundary scan (JTAG) testing through a four-wire Test Access Port (TAP). This simplifies system design and allows standard automatic test equipment to perform both functions. The AC characteristics of the XC18V00 tap are described as follows

Connection Configuration Proms
The data output of the programmable read-only memory drives the DIN input of the lead FPGA device.
The main FPGA CCLK output drives the PROM's CLK input (in main serial and main select map modes only).
The CEO output of the PROM drives the CE input of the next PROM in the daisy chain (if any).
The OE/reset pins of all PROMs are connected to the initialization pins of all FPGA devices. This connection ensures that the PROM address counter is reset before any (re)configuration starts, even when a V fault initiates a reconfiguration as CCNT can drive the PROM CE input from the done pin. The CE input of the first (or only) programmable ROM can be driven by the completion output of all target FPGA devices,
But only if it is not permanently grounded. CE can also be permanently low bound, but this keeps the data output active and results in an unnecessary 10 mA maximum supply current.
Slave Parallel/Select Mapping mode is similar to Slave Serial mode. Data is clocked out of the programmable ROM, one byte per CCLK, rather than one bit per CCLK cycle. See the FPGA datasheet for special configuration requirements.
Start FPGA configuration
The xc18v00 device contains a pin named cf which can be controlled by the jtag config command. When executing the config command through jtag
CF is low for 300–500 ns, resets the FPGA and starts configuration.
To use this feature, the CF pin must be connected to a program pin on the FPGA.
Affecting software can also initiate FPGA configuration by issuing the jtag config command via the "Load FPGA" setting.
The 20-pin package does not have a dedicated CF pin. For the 20-pin package, routing can be done using the CF→D4 setup.
The cf pin works for pin 7 only if the parallel output mode is not used.
Select configuration mode
The XC18V00 supports serial and parallel configuration methods. The configuration mode can be selected through the user control registers in the XC18V00 device. This control register is accessible via JTAG and is set using the "Parallel Mode" setting on the Xilinx Impact software. Serial output is the default configuration mode.
Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and its associated interconnections are established by the configuration program. Programs can be loaded automatically at power-up or on command, depending on the state of the three FPGA mode pins. In master serial mode, the FPGA automatically loads the configuration program from external memory. Xilinx Proms are designed to accommodate master serial mode.
After power-up or reconfiguration, as long as all three FPGA mode select pins are low (m0=0, m1=0, m2=0), the FPGA enters master serial mode. Data is sequentially read from the programmable read only memory on one data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration.
Master serial mode provides a simple configuration interface. Only one serial data line, one clock line, and two control lines are required to configure the FPGA. Data is read sequentially from the programmable ROM, accessed through internal address and bit counters that increment on each valid rising edge of CCLK. If user programmable, the dual function DIN pins on the FPGA are for configuration only and must be kept at specified levels during normal operation. The XilinxFPGA family handles this automatically using on-chip pull-up resistors.
Cascaded configuration proms For multiple FPGAs configured as a serial daisy chain, or for a single FPGA that requires larger configuration memory in serial or select-mapped configuration modes, cascading PROMs provide additional memory
The xc18v00 device can drive the CE input of downstream devices by using the ceo for the cascaded output. The clock input and data output of all XC18V00 devices in the chain are interconnected. After reading the last data of the first PROM, the next clock signal sent to the PROM asserts its CEO output low and drives its data line to the high Z state. The second programmable ROM recognizes a low level on its CE input and enables its data output.
After configuration, all if PROM OE/reset pins, cascade PROM reset.

Reset and power-on reset activation When power-on, the device requires the V supply to rise monotonically to the rated operating voltage within the specified V rise time. If the power supply does not meet this requirement, the device may not perform a power-on reset properly. During energization, CCNTCCNT
oE/reset is held low by the PROM.

Once the required supplies arrive at their respective locations
Por (power-on reset) threshold, OE/reset release delay (tmin) to allow power to stabilize before starting configuration. OER
The OE/reset pin is connected to an external pull-up resistor and also to the initial B pin of the target FPGA. In order for the system to take advantage of the slowly rising power supply, an additional power supply monitoring circuit can be used to delay the target.
Configured to hold the OE/reset pin low until the system power supply reaches a minimum value, resulting in an operating voltage.
When oe/reset is released, the fpga's init_b pin is pulled high, allowing the fpga's configuration sequence to begin. If the power supply falls below the power-down threshold (v) PROM resets and OE/reset remains low again until after the POR threshold is reached. CCPD
OE/reset polarity is not programmable.
For full power platform Flash PROM, a reset occurs.
whenever OE/reset is asserted (low) or CE is de-asserted (high). The address counter is reset, the CEO is driven high, and the remaining outputs are placed in the high z state.
Standby Mode Whenever CE is asserted high, the programmable ROM enters a low-power standby mode. The address is reset. Regardless of the state of the OE input, the output remains in the high-z state. The JTAG pins TMS, TDI and TDO can be in a high-Z state or high.
When using the FPGA DONE signal to drive the PROM CE pin high to reduce the standby power after configuration, an external pull-up resistor should be used. A 330Ω pull-up resistor is typically used, but please refer to the appropriate FPGA datasheet for recommended pull-up values for done pins. If done circuit is connected to an LED to indicate FPGA configuration is complete and also connected to programmable read only memory.
CE pin enables low power standby mode, then an external buffer should be used to drive the LED circuit to ensure a valid Proms transition on the CE pin. If the low power standby PROM does not require mode, the CE pin should be tied to ground. 5V Tolerant I/O The I/O on each reprogrammable PROM is fully 5V tolerant even through a 3.3V core supply. This allows 5V CMOS signals to be connected directly to the inputs of the programmable ROM without damage. Additionally, the 3.3V supply can be applied before or after the 5V signal is applied to the I/O. In a mixed 5V/3.3V/2.5V system, user pins, core power (V), and output power (V) can be powered in any order. This makes the PROM device CCNTCCNTCCO

Customer Control Bits The xc18v00 proms have various control bits accessible to the customer. These can be set after programming the array using "Skip User Array" in Xilinx Impact software. Shock software can set these bits to enable optional JTAG read security, parallel configuration mode, or CF→D4 pin functionality.