illustrate
The WM8501 is a line driver with integrated 1.7VRMS. It is designed for audio applications requiring enhanced load drive capability for high voltage output.
The WM8501 supports data input word lengths from 16 to 24 bits and sampling rates up to 192kHz. The WM8501 includes serial interface port, digital interpolation filter, multi-bit Sigma-Delta modulator in 14 and stereo DAC-lead SOIC package.
The hardware control interface is used to select the audio data interface format, enable and disable emphasis. This WM8501 supports I2S, right justified or DSP interface. Operating the WM8501 on separate analog and digital supplies provides a very low-power digital section while supporting enhanced load-driven analog outputs.
Features 5V Analog Stereo DAC with 1.7Vrms Line Drivers
Provides audio performance
-100dB SNR ('A' weighted @48kHz) - 88db thread
DAC sampling frequency: 8kHz–192kHz
Pin selectable audio data interface format-I2
S, 16-bit right justified or DSP14 lead SOIC package
4.5 V-5.5 V analog, 2.7 V-5.5 V digital power operating application set-top box
DVD
Digital Television

Device Description Overview
The WM8501 is a high performance digital to analog converter with integrated 1.7Vrms line driver from 5V.
Analog power supplies designed for digital consumer audio applications.
The WM8501 is a complete two-channel stereo audio digital-to-analog converter, including digital interpolation filters, multi-bit Sigma Delta with dither, and switched-capacitor multi-bit stereo DAC output smoothing filters. It is fully compatible and is an ideal partner for a range of industry standard microprocessors, controllers and DSPs. Control of the internal functions of the device is provided by hardware control pins (pin programming).
Supports operation using a 256fs, 384fs, 512fs or 768fs master clock, which can be automatically controlled at the clock rate. Sampling rates (fs) below 8kHz to 96kHz are allowed, provided the appropriate system clock is input. The supported frequencies are also up to 192kHz. Use a master clock of 128fs or 192fs.
The audio data interface supports 16-bit right-justified or 16-24-bit I2S (Philips left-justified, one-bit delay) interface format. DSP interface is also supported, enhancing the user.
Split analog and digital 2.7-5.5V supplies are available, and the output amplitude is absolutely scaled to the analog supply level. Low supply voltage operation and low current consumption combined with a low pin count small package make the WM8501 attractive for many consumer applications. - Provides a power-down mode to minimize power consumption. The device is packaged in a small 14-pin SOIC.
DAC circuit description
The WM8501 DAC is designed to allow playback of 24-bit PCM audio or similar high data.
High resolution, low noise and low distortion. Sampling rates up to 192kHz are available, but much lower.
If the ratio of the sample rate (LRCLK) to the master clock (MCLK) is maintained at one of the required rates.
The two DACs on the WM8501 are implemented using Sigma-Delta oversampling conversion.
technology. These require digital filtering and interpolation of the PCM samples to generate a set of samples much higher than input rates up to 192kHz. This example stream is then digitally modulated to produce a stream of digital pulses, which is then converted to a stream of analog pulses.
The signal in the switched capacitor DAC.
The advantage of this technique is that the DAC is linearized using noise shaping techniques.
Allows the use of non-critical analog components to meet 24-bit resolutions. A further advantage is that the high sampling rate of the DAC output means that the output of the DAC only needs to have fairly rough characteristics, which can be removed.
Steps or images on the DAC output. Prevent unwanted pitch dithering Used in digital modulators with higher order modulators.
The multi-bit switched capacitor technique used in digital-to-analog converters reduces clock jitter sensitivity and significantly reduces out-of-band noise compared to switched current or single-bit techniques.
The voltage on the VMID pin is used as the reference voltage for the DAC. Therefore, the signal at the output of the amplitude DAC will scale with the amplitude of the voltage at the VMID pin. An external reference can be used to drive to the vmid pin if desired, with a value usually for best performance on the mid rail.
The outputs of the 2 digital-to-analog converters are buffered out of the device by a buffer amplifier that can be driven.
Low impedance line loads as low as 820 and headphone loads as low as 16. The amplifier output voltage level for line level loads is set to 1.7 volts rms when the buffer is using 5 volts analog.
provided, avoiding the need for additional gain stages or higher power supply applications in many cases. When the driver headphone is loaded, the output voltage level is limited to 1Vrms. This advanced multi-bit digital-to-analog converter used in the WM8501 produces far less out-of-band noise than single-bit digital-to-analog converters.
Traditional sigma-delta-dacs, etc., in most applications requiring row-level output, do not require post-DAC filters. Usually an AC coupling capacitor and a DC setting resistor to ground are the only components required for the chip output.

Clocking Schemes In a typical digital audio system, there is only one central clock source that generates the reference clock.
All audio data processing is synchronized to. This clock is often referred to as the master clock of the audio system. An external master clock can be applied directly through the MCLK input.
There is no sampling rate to select the pins of the desired configuration.
Note that on the WM8501, MCLK is used to derive the clock for the DAC path. The DAC path consists of the DAC sampling clock, the DAC digital filter clock, and the DAC digital audio interface timing. In a situation where there are many possible sources for the reference clock, it is recommended to use the clock source with the least jitter to optimize the performance of the DAC.
By stopping MCLK, the device can be powered down. In this state, power consumption is greatly reduced.
Digital Audio Interface Audio data is applied to the internal DAC filter through the digital audio interface. Three interface supported formats: right-justified mode
All formats in DSP mode are sent MSB first. The data format is selected via the format pin. If low when formatting, a right-justified data format is selected, and a word length of 16 bits can be used. When the format PIN is high and the S format is selected, the word length of any value can be used up to 24 bits. (If the used word length is less than 24 bits, the unused bits should be padded with zeros).
If LRCLK is 4 BCLKs or less in duration, select a DSP-compatible format. Mode A and Mode B clock formats are supported, selected by the state of the format pin.
"Packed" mode (that is, only supports 32 or 48 clocks per LRCLK cycle) operation is also supported in both I2s.
(16-24 bits) and right justified format (16 bits). If a "packed" format of 16-bit word length is applied (16 BCLKs per LRCLK half cycle), the device automatically detects this mode and switches to 16-bit data length.
WM8501 supports word length of 16-24 bits in I2
In S mode, the digital audio interface receives data input. Audio data is time multiplexed with LRCLK, indicating whether a left or right channel is present. LRCLK is also used as a time reference to indicate the start or end of a data word.
In S mode, the minimum number of BCLKs per LRCLK cycle is 2 times the length of the selected word. lrclk must be high (minimum word length) bclks, low (minimum word length) bclks.
length bclks. Any mark-to-space ratio on LRCLK is acceptable if the above requirements are met.
Satisfy. In S mode in I2, on the second rising edge of BCLK, the MSB is sampled after LRCLK.
transition. lrclk is lower when sampling left, and higher when sampling right.

right-aligned mode
The WM8501 supports a word length of 16 bits in right-justified mode.
In right-justified mode, the digital audio interface accepts data input. Audio data is time multiplexed with LRCLK, indicating whether a left or right channel is present. LRCLK is also used as a time reference to indicate the start or end of a data word.

In right-justified mode, the minimum number of BCLKs per LRCLK cycle is 2 times the word length of the selected time. lrclk must be at least word length bclks high and at least low word length bclks. If the above occurs, any mark-to-space ratio on LRCLK is acceptable.
fulfil requirements.
In right-justified mode, the LSB is sampled on the rising edge of BCLK before LRCLK.
transition. lrclk is high for left sampling and low for right sampling.
Right Justified Mode Timing Diagram

The WM8501 also supports a time division multiplexing format compatible with DSP. This format refers to the type of "sync" pulse followed by two predetermined data words (left and right).
word length. (16 bits). The "sync" pulse replaces the normal duration LRCLK, and the DSP mode is auto-detected from the shorter normal duration of the LRCLK. If lrclk is equal to or less than 4 bclk duration, select a DSP compatible format. Mode A and Mode B clock formats are supported, selected by the state of the format pin.

Audio data sample rate
The main clock of the WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCLK), typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. This master clock is used to operate digital filters and noise shaping circuits.
The WM8501 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sample rate (within +/- 8 master clocks). If there is an error greater than 8 clocks, the interface shuts down the DAC and mutes the output. This master clock should be synchronized to LRCLK, although the WM8501 allows for differences or jitter in the phase clock.

hardware control mode
The WM8501 is hardware programmable and provides the user with the option to select input audio data.
Format, de-emphasize and mute.
enable action

Pin 4 (enable) controls the operation of the chip. If enable is low, the device remains in a low power state. If this pin is held high, the device is powered.
To ensure proper operation, there must be a low-to-high transition on the enable pin. After the digital power is turned on. This can be done by providing it from an external controller chip or by a simple RC network on the enable pin. See "Recommended External Components" in the "Application Information" section at the end Note that the enable pins should not be used as mute pins or to temporarily mute the DAC.
(eg, between tracks of a CD). Enable pins cannot be used as mute.
control, but allows entry into low power mode. Disabling the device by enabling the pin has the effect of shutting down the voltage on the VMID pin. Repeated enabling/disabling of the device will make a ping sound at the output.

Application Information Recommended External Components External Parts Diagram In applications where the enable is powered directly from VDD instead of a dedicated control line, resistor R3 and capacitor C9 are used on the enable pin to transition from low to high on enable. This will ensure the pins go high after the power has time. Settlement (see "Enable Operation" in the "Hardware Control Mode" section of the datasheet). However, if the enable signal is provided directly from an external controller chip instead of VDD, R3 and C9 are not required.