The EL7536 is a synchronous, integrated FET 1A buck regulator with internal compensation. It has an input voltage range of 2.5V to 5.5V and can accommodate 3.3V, 5V or Li-Ion battery power. The output is externally programmable from 0.8V to VIN via a resistive divider. EL7536 has PWM mode control function. The operating frequency is usually 1.4MHz. Other features include 100ms power-on reset output, <1µA shutdown current, short-circuit protection and over-temperature protection. The EL7536 is housed in a 10-pin MSOP package, which allows the entire converter to occupy less than 0.15in2 of PCB area, providing components only on one side. Both packages can operate over the full temperature range of -40°C to +85°C.

The EL7536 is a synchronous integrated FET 1A step-down regulator that operates from an input voltage of 2.5V to 6V. The output voltage can be adjusted by the user through a pair of external voltages. Resistor. The internal compensation controller enables the use of only two ceramic capacitors and one inductor to form a complete 1A DC:DC converter with a very small footprint. Startup and Shutdown When the en-pin is tied to VIN, VIN reaches about 2.4V and the regulator starts switching. This output voltage is ramped up to ensure proper soft-start operation. When the EN pin is tied to logic low, the EL7536 is in shutdown mode. All control circuits and MOSFETs are turned off and VOUT drops to zero. In this mode, the total input current is less than 1 µA. When en reaches logic hi, the regulator repeats the start-up procedure, including the soft-start function.

The EL7536 is a synchronous, integrated FET1A buck regulator that operates from a 2.5V to 6V input. This output voltage is user adjustable with a pair of external resistors. Internal compensation controller capable of using only two ceramic capacitors and one inductor to form a complete, very small footprint 1A DC:DC converter.

startup and shutdown

The regulator starts switching when the EN pin is connected to VIN and VIN reaches about 2.4V. This output voltage is gradually increased to ensure proper soft-start operation. When the EN pin is connected to a logic low level, the EL7536 is in shutdown mode. All control circuits and both MOSFETs are cut off and VOUT drops to zero. In this mode, the total input current is less than 1µA. When EN reaches a logic high level, the regulation repeats the start-up procedure, including the soft-start function.

PWM operation

In PWM mode, P-channel MOSFET and N-channel MOSFET always work complementary. When the PMOSFET is turned on and the NMOSFET is turned off, the inductor current increases linearly. The input energy is transferred to the output, also stored in the inductor. When the P-channel mosfet is turned off and the n-channel mosfet is turned on, the inductor current decreases linearly and energy is drawn from the output inductor. Therefore, the average current through the inductor is the output current. Because the inductor output capacitance acts as a low-pass filter, the cycle ratio is approximately equal to vo divided by vin. The output LC filter has a second order effect. To maintain converter stability, the entire controller must be compensated. This is done through an internal fixed compensation error amplifier and PWM compensator. Because the compensation is fixed, the input value output capacitors are 10µF to 22µF ceramic. This inductance is nominally 1.8µh, but 1.5µa to 2.2µh can be used.

100% duty cycle operation The EL7536 uses a CMOS power field effect transistor as an internal synchronous power switch. The upper switch is PMOS and the lower switch is NMOS. This not only saves the boot capacitor, but also can turn on the switch of the upper PFET 100%, so that VO is close to VIN. The maximum achievable VO is, VO=VIN–(RL+RDSON1)×IO, where RL is the DC resistance of the inductor and R DSON1PFET on-resistance, nominally 70mΩ at room temperature with a temperature coefficient of 0.2mΩ/°C content. When the input voltage gradually drops close to even the preset VO, the converter enters a 100% duty cycle. Under this condition, the upper PFET needs a certain minimum off time if it is turned off. This off-time is related to input/output conditions. This makes the duty cycle appear to randomly increase the output ripple somewhat until 100% duty cycle is reached. Larger output capacitors can reduce random-finding ripple. The user needs to verify if this condition holds the entire circuit and if the adverse effects of the duty cycle near 100% are more than expected.