General Instructions

. In essence, this part can mainly operate Mode A and B in alternate configurations – Mode A provides switch controller to generate 5Vdl from ATX power supply, linear controller – str1 (2.5Vdual) and bus terminator controller – 1.25 Vdual , for high-speed buses such as RDRAM/DDRAM current sinks and sources; Mode B offers to design a switch controller that generates a 5Vdl voltage from the ATX power supply, and three linear controllers for specific voltage regulation - i.e. str1 (2.5Vdl ), str2 (3.3Vdual) and str3 (1.8Vdual), all outputs can be configured simply by vset0, vset1. In addition, the W83301R can provide up to 0.2V of additional voltage in each regulator output for improved performance. In order to reduce the customer's cost and simplify the circuit design, the W83301R integrates a charge pump engine in the chip to provide a higher driving voltage for a single N-channel MOSFET (ie W83301R), which can only drive the N-channel MOSFET for all applications. On the other hand, the W83301R also provides PWOK and overcurrent detection to protect each output and soft start to protect all linear controllers from inrush current attacks. The W83301R is packaged in a 20-pin SOP.
Features provide optional configurations for flexible applications
A mode provides a switch controller to generate 5vdual
Linear controller str1–2.5vdual (RDRAM/DDRAM application)
Bus Termination Controller - 1.25V dual channel for high speed bus termination applications to sink and acquire redundant current Mode B
Provides a switch controller to generate 5vdual
Linear controller str1 – 2.5vdual (clock generation application) Linear controller str2 – 3.3vdual (SDRAM application)
Linear controller str3 – 1.8vdual (chipset application)
A switch is provided to enable/disable the 5vdl output in the S5 state via the 5vdlen pin of the USB application.
Supports SDRAM/RDRAM/DDRAM ACPI-STR function Drives all N-channel MOSFETs Powers up all controllers Soft-start For overclocking applications, delta voltage on str1/str2 is up to 0.2V.
Undervoltage fault monitor soft-start function 20-pin SOP package pin configuration Figure 1. W83301R pin configuration

Application circuit

Application Circuit Mode B (SDRAM Mode) Application Circuit

Block Diagram W83301R Internal Block Diagram

Function description mode selection
W83301R supports two modes for customer multi-application, as shown in Table 1, mode A and mode B can be selected by VSET0 pin. If this pin is connected to 5V, the chip will work in mode A, otherwise when VSET0 is connected to ground, the chip will work in mode B.
Both Mode A and Mode B support linear switching and generate ACPI compliant 5VDL voltage from ATX power supply 5V/5VSB according to S5 and S3 signals. The user can also turn off the entire 5vdl output in the S5 state through the 5vdlen_pin as needed.
In Mode A operation, the chip provides a linear controller str1 that drives an n-channel MOSFET q3 (see diagram) to generate a regulated voltage 2.5vdual from an external power supply 3.3vdual, 2.5vdual for RDRAM/DDRAM ACPI suspend to RAM application. In order to simplify circuit design and reduce user cost, W83301R also integrates a bus termination controller BT to drive two external N-channel MOSFETs (Q4, Q5) to generate a specific ACPI compatible voltage based on half of str1 output to acquire and sink Bus redundancy current.
In Mode B operation, the chip provides three linear controllers, str1-2.5vdual, str2-3.3vdual, and str3-1.8vdual, with all three outputs driving an nchannel mosfet (q3, q4, and q5) through different applications Generates ACPI compliant voltages. For example, str1-2.5vdual for clock generator applications str2-3.3vdual for SDRAM applications, str3-1.8vdual for chipset applications.
In addition, as shown in Table 1, the W83301R also provides a tri-state pin VSET1, which enables an extra voltage of up to 0.2V in each output to improve performance, but in Mode A operation, the BT output voltage will be based on str1 set by VSET1 Half of the output is generated.

ACPI State Control To meet the ACPI specification, the W83301R implements a state machine, as shown in Figure 5, to generate ACPI compliant power state transitions.
There are only five states in the state machine, because W83301R only focuses on memory ACPI control, the five states are G3 (mechanical off state), S0 (full power state), S3 (sleep state suspended to RAM), S5ON (soft off state) state), S5OFF, all of which change depending on the state of S3, S5, and 5vdlen. On the other hand, the reason for the W83301R allows customers to disable/enable the 5vDual output in the S5 state via the 5vdlen_pin, there are two states: S5on and S5off, corresponding to the S5 state. During the S5off to S5on state transition, a soft ramp mechanism is required to protect the 5vdl output from inrush current attacks. Same as the 5vdl output, the W83301R also provides a soft-climbing mechanism during the s5on to s0 state transition of each str output.
In the state machine, when the power is turned on and the 5V voltage of the power input reaches 4.5V, the chip first enters S5OFF from G3, and rises to the S5ON state by two conditions. One condition is that 5vdlen=0 under the backup power supply restores the 5vdl output. Another condition is that S3=1 and S5=1, the system enters S1 state.
In the s5on state, when the customer wants to disable the 5vsb output (5vdlen=1) to save some power, the chip will go back to s5off. The chip will drive all outputs into S0 state, S3=1 and S5=1.
When the system is in the S0 state, when the system is idle for a long time or the user is powered off, the system should enter the S3 sleep (S3=0, S5=1) or S5 soft-off (S5=0) state.
When the system suspends to RAM, the system will wake up and enter the S0 full power state via (s3=1, s5=1, pwok=1), or enter the S5 sleep soft-off state via (s5=0).

Charge Pump To simplify the design of the circuit and provide customers with a good price solution, the W83301R integrates a switched capacitor voltage multiplier charge pump to provide higher drive voltages (up to 10V) and can drive the A single N-channel MOSFET.
power ok
The W83301R uses a bidirectional power supply OK signal to ensure that the system works properly. When the system jumps from state S3 to state S0, the W83301R will monitor the input signal from the PWOK pin to ensure that the external system power supply is normal, and then switch each output to the S0 level; on the other hand, the W83301R will pull down the power supply OK signal, Notifies the system of overcurrent and sensed undervoltage.
Soft Start During the "s5off" to "s5on" and "s5on" to "s0" state transitions, the 5vdual and str voltages need to be ramped from 0 to their set values, respectively. The charging current flowing into the output capacitor must be limited to avoid supply droop.
In the W83301R, an internal 18uA current source (ISS) charges an external capacitor (CSS) to generate a linearly rising voltage on the SS pin (VSS). During the above state transitions, the vss transitions from 0 to about 9V, and the vss transition rate is used to limit the rise rate of the 5vdual and str output voltages. This output hold allows for a power down event of the uninterruptible power supply.
Since the output rises at a constant slew rate, the current used to charge any output capacitor can be calculated using the following formula: icout=iss x(cout/css)
The W83301R also employs some techniques to further reduce the total charge current: In Mode B configuration, the start-up of the ramp-up time str3 (1.8V) will be advanced from str1 to reduce the overlapping time of charging. In the Mode A configuration, the bus terminator is input clamped and its output voltage slew rate and charge current will be limited to half of str1.
Note that too slow a ramp rate is not recommended. If so, the above-mentioned national transition will be extended to a great extent. The state transition will not complete and the next state will not be entered until VSS has risen to its upper limit (about 9V).

Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid applying any voltage above the maximum rated voltage to this circuit. Exposure to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to the appropriate logic voltage level (ground or VDD)