The AD7714ARS-5 is a complete analog front-end measurement application for low frequencies. The device accepts a low level signal directly from the transducer and outputs a serial digital word. It uses sigma-delta conversion technology to achieve up to 24 bits without loss of code performance. The application input signal is based on a proprietary programmable gain front end analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed through on-chip control registers, allowing adjustment of filter cutoff and settling times. The device has three differential analog inputs (which can also be configured as five pseudo-differential analog inputs) and a differential reference input. It operates from a single supply (+3 9251 ; V or +5␣V). Therefore, the AD7714 can perform conversions for all signal conditioning systems with up to five channels.

The AD7714 is ideal for use in smart, microcontroller or DSP systems. It has a configurable serial interface REV. The information provided by CADI is believed to be accurate and reliable. However, Analog Devices assumes no responsibility for its use, nor does it infringe any patents or other rights of third parties which may arise from its use. No license is implied or otherwise under any patent or patent rights of Analog Devices. For three-wire operation. Gain settings, signal polarity and channel selection can be configured in software using the serial port. The AD7714 offers self-calibration, system calibration and background calibration options, and also allows the user to read and write on-chip calibration registers. The CMOS structure ensures extremely low power consumption. The power saving mode reduces standby power consumption to 15␣μW typical. The device is available in a 24-lead, 0.3-inch wide plastic Dual In-Line Package (DIP); 24-lead Small Outline (SOIC) package, 28-lead Shrink Small Outline Package (SSOP), and a24-lead Thin Shrink Small Outline Package (TSSOP).

Product Highlights

1. Besides, AD7714Y also provides the following functions

Standard AD7714: Wider temperature range, Schmitt trigger on SCLK and DIN, operating voltage as low as 2.7 V, lower power consumption, better linearity and availability of 24-lead TSSOP package.

2. The AD7714 consumes less than 500 μA (fCLK IN = 1␣MHz) or a total supply current of 1 m (fCLKIN = 2.5␣MHz). It is ideal for loop-powered systems.

3. The programmable gain channel allows the AD7714 to accept signals directly from strain gage or sensor inputs eliminating a large amount of signal conditioning.

4. The AD7714 is ideal for microcontroller or DSP processors. Applications with a three-wire serial interface reduce the number of interconnect lines and reduce the number of optocouplers required for an isolated system. This section contains on-chip registers that allow control of filter cutoff, input gain, channel selection, signal polarity and calibration mode.

5. The part has excellent static performance specifications with 24-bit no missing codes, ±0.0015% accuracy and low rms noise ( 140 nV). The effects of endpoint error and temperature drift are eliminated through on-chip self-calibration, which eliminates zero-scale and full-scale errors.

Feature Function Block Diagram

Charge Balance ADC 24-Bit No Lost Code 0.0015 % Nonlinear Five-Channel Programmable Gain Front-End Gains From 1 to 128 Configurable as Three Fully Differential Inputs or Five Pseudo-Differential Inputs DSP Compatible 3 V (AD7714-3) or 5 V (AD7714-5) Operation Low Noise (<150 nV rms) Low Current ( 350 ␣mA Typical), Power-Down (5 mA Typical)

AD7714Y grade:

+2.7 V to 3.3 V or +4.75 V to +5.25 V operation 0.0010% linearity error -408C to +1058C temperature range Schmitt trigger SCLK and DIN Low current ( 226 ␣mA typical) with power-down function (typ. 4 mA) Lower power consumption than standard AD7714 Available in 24-lead TSSOP package Low-pass filter with programmable filter cutoff frequency Ability to read/write calibration coefficients.

application

Portable Industrial Instruments

Portable Weighing Scale

loop powered system

Pressure Sensor

PIN configuration diagram

AD7714-5 output noise

Table 1a lists the typical notch and output rms noise and effective resolution of the AD7714-5 at -3␣dB frequencies

fCLK␣IN=2.4576␣MHz, and Table 1b gives the information of fCLK IN =1␣MHz. Figures given are typical for a bipolar input range VREF of +2.5␣V and BUFFER = 0, generated at an analog input voltage of 0␣V.

The numbers in parentheses in each table are used to indicate the effective resolution of the part (rounded to the nearest 0.5␣LSB). The voltage of a valid solution device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/GAIN). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be up to 6.6 times the rms number and the effective resolution numbers based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise as quoted in the table.

The output noise of this part comes from two sources. The first is the implementation of electrical noise modulators for semiconductor devices (device noise). Second, quantization noise increases when the analog input signal is converted to the digital domain. Device noise is low and largely independent of frequency. Quantization noise starts at even lower levels but rises rapidly with increasing frequency, becoming the dominant noise source. Therefore, lower filter notch settings (about 100 ␣ Hz for fCLK IN = 2.4576 ␣ MHz, and 40 ␣ Hz for fCLK IN = 1 ␣ MHz) tend to favor device noise dominance, while higher notch The wave setting is mostly quantization noise. Changing the filter notch and cutoff frequencies in the quantization noise-dominant region results in a more significant improvement in noise performance than in the device noise-dominant region as shown in Table I. Furthermore, quantization noise is added after the PGA, so the effective resolution is largely independent of gain for higher filter notch frequencies. At the same time, device noise is added to the PGA, so for lower notch frequencies, the effective resolution is reduced. Furthermore, in the device noise dominated region, the output noise (in μV) is largely independent of the reference voltage, whereas in the quantization noise dominated region, the noise is proportional to the value of the reference. The device can be post-filtered to increase a given output data rate

The -3␣dB frequency can also further reduce the output noise.

AD7714-3 output noise

Table IIa shows the output rms noise and effective resolution fCLK␣IN = 2.4576␣MHz for some typical notches and -3␣dB frequencies of the AD7714-3, while Table IIb gives the information for fCLK IN = 1␣MHz. The numbers given are bipolar inputs

VREF is the range of +1.25␣V and BUFFER = 0. These figures are typical values and are generated at an analog input voltage of 0␣V.

The numbers in parentheses in each table represent the effective resolution of the part (rounded to the nearest 0.5␣LSB). efficient

The resolution of the device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/GAIN). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise figure can be as high as 6.6 times the rms figure, while the peak-to-peak noise based effective resolution figure can be 2.5 bits lower than the rms based effective resolution of the noise quoted in the table.

The output noise of this part comes from two sources. The first is the implementation of electrical noise modulators for semiconductor devices (device noise). Second, quantization noise increases when the analog input signal is converted to the digital domain. Device noise is low and largely independent of frequency. Quantization noise starts at even lower levels but rises rapidly with increasing frequency, becoming the dominant noise source. Therefore, lower filter notch settings (about 100 ␣ Hz for fCLK IN = 2.4576 ␣ MHz, and 40 ␣ Hz for fCLK IN = 1 ␣ MHz) tend to favor device noise dominance, while higher notch The wave setting is mostly quantization noise. Changing the filter notch and cutoff frequencies in the quantization noise-dominant region results in a more significant improvement in noise performance than in the device noise-dominant region as shown in Table II. Furthermore, quantization noise is added after the PGA, so the effective resolution is largely independent of gain for higher filter notch frequencies. At the same time, device noise is added to the PGA, so there is a high gain in effective resolution for lower notch frequencies. Furthermore, in the region dominated by device noise, the output noise (in μV) is largely independent of the reference voltage, while in the region dominated by quantization noise, the noise is proportional to the reference value. The device can be post-filtered to increase a given output data rate - 3␣dB frequencies can also further reduce output noise.

The AD7714 contains eight on-chip registers that can be accessed through the device's serial port. The first one is the register selected by the communication control channel that decides whether the next operation is a read or write operation, and decides it registers for the next read or write operation access. All communications with the device must begin with a write to the device. After power-up or reset, the device needs to write to the communication register. Data Written This register determines whether the next operation to the device is a read or write operation, and determines which register this read or write operation takes place. Therefore, a write access to any other register on the device begins with a write to that device after the communication register is written to the selected register. A read from any other register on the device, including the output data register, begins with a write to the communications register, followed by a read from the selected register. The communication register also controls the channel selection, and the DRDY status can also be read to obtain the communication register. The second register is the mode register, which determines the calibration mode and gain settings. The third register, labeled Filter High Register, determines the word length, bipolar/unipolar operation and contains the upper 4 bits of the filter select word. The fourth register, labeled Filter Low Register, contains the low 8-bit word of the filter selection. The fifth register is the test register and can be accessed when testing the device. The sixth register is the output data of the data register access unit. The final register allows access to the device's calibration registers. Zero scale

The calibration registers allow access to the zero-scale calibration coefficients for the selected input channel during full-scale calibration. The registers allow access to the full-scale calibration coefficients for the selected input channel. Registers are discussed in more detail in the following sections.

Communication Register (RS2-RS0 = 0,0,0)

The communication register is an 8-bit register from which data can be read or written. All communications in this section must begin with a write to the communications register. The data written to the communication register determines whether the next operation is a read or write operation and in which register the operation occurs. Once a subsequent read or write operation to the selected register is complete, the interface returns to the communication register where it expects the write operation. This is the default state of the interface. After power-on or reset, the AD7714 is in this default state waiting for a write to the communication register. In the event of a loss of interface sequence, the AD7714 returns to this default state if a write operation is performed with DIN high for a sufficient duration (comprising at least 32 serial clock cycles). Table V summarizes the bit assignments for the communications registers.

circuit description

The AD7714 is a sigma-delta A/D converter with on-chip digital filtering for measuring wide dynamic range, low frequency signals such as weighing, pressure sensors, industrial control or process control applications. It contains a sigma-delta (or charge balance) ADC, a calibrated microcontroller with on-chip static RAM, a clock oscillator, digital filters, and a bidirectional serial communication port. The device consumes only 500µA of supply current and requires only 10µA in standby mode, making it ideal for battery-powered or loop-powered instruments. The device is available in two versions, the AD7714-5, which is specified for operation from a nominal +5␣V analog supply (AVDD), and the AD7714-3, which is specified for operation from a nominal +3.3␣V analog supply. Both versions can operate from a digital supply (DVDD) voltage of +3.3␣V or +5␣V. The AD7714Y grade part operates from a nominal AVDD of 3 V or 5 V, and can operate from a digital supply of 3 V or 5 V. The device Contains three programmable gains fully differential

The analog input channels can be reconfigured as five pseudo-differential inputs. All channels have a gain range of 1 to 128, allowing the section to accept unipolar signals between 0 mV to +20␣mV and 0 V to +2.5␣V. In bipolar mode, the part handles normal bipolar signals of ±20 mV and quasi-bipolar signals up to ±2.5 V when the reference input voltage is equal to.

+2.5␣V. The reference voltage is +1.25␣V, the input range is from 0 mV to +10 mV to 0 V to +1.25␣V in unipolar mode, in bipolar mode, the device can handle true bipolar signals ±10 mV and quasi-bipolar signals, up to ±1.25 V. This part uses sigma-delta conversion technology to achieve up to 24 bits without missing codes. sigma-delta

The modulator converts the sampled input signal into digital pulses whose duty cycle contains the train of digital information. The programmable gain function on the analog input is also combined by input sampling in this sigma-delta modulator where the frequency of the modulator is modified to give higher gain. A sinc3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the filter's first notch frequency. This output data can be read randomly or periodically from the serial port anyway higher than the output register update rate. The first notch of this digital filter, its -3␣dB frequency and its output rate can be programmed through the filter high and low filter registers. The master clock frequency is 2.4576 MHz, and the first notch frequency and output are programmable ranging from 4.8␣Hz to 1.01 kHz, giving a programmable range of 1.26 Hz to 265␣Hz for -3␣dB frequencies. The basic connection diagram of the device is shown in the figure below. This means that both the AVDD and DVDD pins of the AD7714 are driven by an analog +3␣V or +5␣V supply. Some applications will use separate supplies to drive AVDD and DVDD. inside

As shown, the analog inputs of the AD7714 are configured as three fully differential inputs. This section has set the unbuffered mode for these analog inputs. An AD780, precision +2.5 V reference, provides the reference source section. On the digital side, the part is configured for operation with a three-wire CS connected to DGND. A quartz crystal or ceramic resonator provides the main clock source for the device. It is possible that a capacitor on the crystal or resonator must be connected to ensure that it does not oscillate in the overtones of its underlying operating frequency. The value of the capacitor will vary according to the manufacturer's specifications.

The AD7714 contains six analog input pins (labeled AIN1 to AIN6) that can be configured as three fully differential input channels or five pseudo-differential input channels. The CH0, CH1, and CH2 configuration of the bit communication registers The analog input arrangement and channel selection are as previously outlined in Table VII. Input pairs (differential or pseudo-differential) provide programmable gain, and the inputs can handle channel signals from unipolar or bipolar inputs. It should be noted that bipolar input signals are referenced to the corresponding AIN (-) inputs of the input pair. In unbuffered mode, the common-mode range of these inputs is from AGND to AVDD providing the absolute value of the analog input voltage between AGND␣-␣30␣mV and AVDD +30␣mV. This means that in unbuffered mode, the part can handle both

Unipolar and bipolar input ranges for all gains. In buffered mode, the analog input can handle a larger source impedance, but the absolute input voltage range is limited between AGND␣+50␣mV to AVDD - 1.5␣V. A common-mode range limit can also be placed. This means that buffer mode has some limitations on the allowable gain for bipolar input ranges. Care must be taken when setting the common mode voltage and input voltage range so that the upper limit is not exceeded, otherwise degraded linearity performance will occur. In unbuffered mode, the analog input goes directly to the 7␣pF input sampling capacitor, CSAMP. The DC input leakage current in this unbuffered mode is a maximum of 1␣nA. The result is that the analog input sees a dynamic load at the input sample rate (see figure below). This sample rate depends on

Master clock frequency and selected gain. CSAMP is charged to AIN(+) and discharged to AIN(-) every input sampling period. The effective on-resistance RSW of the switch is typically 7␣kΩ

Unbuffered analog input structure

The programmable features of the AD7714 are controlled using a set of on-chip registers as previously described. Data is written to these registers through the device's serial interface and read access to the on-chip registers is also provided by this interface. All communications This section must start the communications registration with a write operation. After power-up or reset, the device expects to write to its communication registry. Data written to this register determines whether the next operation on this part is a read or write operation, and also decides to register the read or write operation. Therefore, a write access to any other register on the part starts with a to write the operation to the communication register, and then executes a to write to the selected register. A read operation of any register begins with a write operation to the communication register in part (including the output data register), followed by a read operation from the selected register.

The serial interface of the AD7714 consists of five signals CS, SCLK, DIN, DOUT and DRDY. The DIN line is used to transfer data to the on-chip registers on the DOUT line for accessing data from the on-chip registers. SCLK is the device's serial clock input and all data transfers (either on DIN or DOUT) take place on this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the AD7714's data register. DRDY goes low when there is a new word of data in the output register. When a read operation is performed from the data register, it is reset high and completed. It also registers high before updating the output to indicate when not to read from the device to ensure that no attempt is made to read the data when the register is updated. CS is used to select a device. It can be used to decode AD7714 systems suitable for connecting multiple components to a serial bus.

The AD7714 serial interface can operate in three-wire mode by connecting the CS input low. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the AD7714 and the AD7714 can obtain the status of the DRDY communication register by interrogating the MSB.

Figures 6 and 7 show the timing diagrams for interfacing the AD7714 with CS to decode the device. Figure 6 is a readout diagram showing the operation of the output shift register of the AD7714. Figure 7 shows a write operation to the input shift register. Both diagrams are for a logic high level of the POL input; for operating the POL input at a logic low level just invert the SCLK waveform as shown. The same data can be read even if the DRDY line doubles the output register and returns high after the first read operation. Care must be taken, however, to ensure that the read operation has completed just before the next output update occurs. The serial interface can be reset in this regard by executing the RESET input. It can also reset the DIN input by writing a series of 1s. If a logic 1 is written to the AD7714 DIN line the serial interface is reset for at least 32 serial clock cycles. This in a three-wire system ensures that if an interface is lost, also through a software bug or some glitch in the system, it can reset back to a known state. This state returns the interface AD7714 expects to write to the communication register. This operation itself does not reset the contents of any registers, but since the interface is lost, the information written to any register is unknown and it is recommended to set all registers again.

Read Cycle Timing Diagram (POL = 1)

Write Cycle Timing Diagram (POL = 1)