feature
5 ns pin-to-pin logic delay for system frequencies up to 178 MHz
36 macrocells, 800 usable gates in small form factor package
44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins)
48-pin CSP (36 user I/O pins)
64-pin VQFP (36 user I/O pins)
All packages are lead free Optimized for high performance 3.3V systems low power operation
5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V signals
3.3V or 2.5V output capability Advanced 0.35-micron feature size CMOS Fast Flash™ technology Advanced system functions Programmable in-system Superior pin locking and routability
Fast Connect™ II Switch Matrix Ultra-Wide 54-Input Function Block Up to 90 Product Terms per Macrocell, Each Product Term Assigned Local Clock Inversion with Three Global and One Product Term Clock Inversion Individual Output Enables for Each Output Pin Input lag on all user and boundary scan inputs Bus hold circuitry on all user pin inputs Full IEEE Standard 1149.1 boundary scan (JTAG)
Fast concurrent programming Slew rate control for a single output Enhanced data security features Superior quality and reliability Duration over 10,000 program/erase cycles
20 Years Data Retention Over 2000V ESD Protection Pinout Compatible with 5V Core in XC9536 Devices
44-pin PLCC and 48-pin CSP packages Warning: Programming temperature range Ta=0°C to +70°C
describe
The XC9536XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in high-end communications and computing systems. It consists of two 54V18 function blocks, providing 800 usable gates with a propagation delay of 5ns.
power estimation
Power dissipation in CPLDs can vary widely depending on system frequency, design application, and output load. To reduce power consumption, each macrocell in the XC9500XL device can be configured in a low-power mode (from the default high-performance mode). In addition, the software automatically deactivates unused product terms and macrocells to further save power.
For a general estimate of ICC, the following equation can be used:
ICC(MA)=mchs(0.175* pths +0.345)+mclp(0.052*ptlp)
+0.272)+0.04*mctog(mchs+mclp)*f, where:
mchs=macrocells in high-speed configuration pths=average high-speed product terms per macrocell mclp=macrocells in low-power configuration ptlp=average low-power product terms per macrocell F=maximum clock frequency mctog= Average percentage of toggle flip-flops per clock (~12%)
This calculation is based on lab measurements of an XC9500XL part that populates a 16-bit counter and allows a single output (LSB) to be enabled. Actual ICC values vary by design application and should be verified during normal system operation.

notes:
1. The maximum DC undershoot below ground must be limited to 0.5V or 10mA, whichever is easier to achieve. During conversion, if the overshoot or undershoot duration is less than 10 ns and the current limit is forced to 200 mA, the device pins may undershoot to -2.0 V or overshoot to +7.0 V. External I/O voltage must not exceed VCCInt 4.0V.
2. Stresses in excess of the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and do not imply functional operation of the device under these or any other conditions. Prolonged exposure to absolute maximum rating conditions may affect device reliability

notes:
1. For the lead-free version of the package, the pinout is the same.

notes:
1. Due to the small size of the chip scale packages, the part markings on these packages do not match the samples above, and the markings cannot contain the full part number. Part marking on chip scale packaging:
Row 1 = X (Xilinx logo), followed by the truncated part number (no XC), which is 95XXXL.
Line 2 = Not relevant to device part number.
Line 3 = Not relevant to device part number.
Row 4 = Package code, speed, operating temperature, three digits not related to part number. Package code: C1=CS48, C2=CSG48.