Features Cypress Premis 8482 ; Series Products Generates an EMI-optimized clock signal at the output Selectable input and output frequencies 3.3V or 5V supply operation Low power CMOS design Available in 8-pin Small Outline Integrated Circuit (SOIC) or 14-pin Thin Shrink Small Outline Package (TSSOP select option only)

Overview
The W181 product is a series of equipment in the Cypress Premix range. The premis series incorporates the latest advances in pll spread spectrum synthesizer technology. Frequency modulation of the output with a low frequency carrier greatly reduces peak electromagnetic interference. Using this technique, systems can pass increasingly difficult EMI tests without resorting to expensive shielding or redesign.
In a system, EMI is reduced not only in different clock lines, but also in all signals that are synchronized to the clock. Therefore, the benefits of using this technique increase with the number of address and data lines in the system.
Function description
The W181 uses a Phase Locked Loop (PLL) to frequency modulate the input clock. The result is an output clock whose frequency sweeps slowly across a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed into the phase detector. The signal from the VCO is divided by P and fed back to the phase detector. The phase-locked loop will force the frequency of the VCO output signal to change until the split-phase output signal and the split-phase reference signal match at the phase detector input. The output frequency is equal to the ratio of p/q times the reference frequency. (Note: For the W181, the output frequency is equal to the input frequency.) The unique feature of the spread spectrum frequency timing generator is that the modulation waveform is superimposed on the input of the VCO. This causes the VCO output to slowly sweep across a predetermined frequency band.
Since the modulation frequency is typically 1000 times slower than the base clock, the spread spectrum process has little impact on system performance.

In spread spectrum timing generation, the reduction in EMI depends on the shape of the modulation waveform, modulation percentage and frequency. The frequency range can be set when the shape and frequency of the modulation waveform are fixed for a given value using the frequency select bits (fs1:2 pins). The paving percentage was set to 1.25% or 3.75% (see Table 1).
A larger spread percentage improves EMI reduction. However, larger scaling percentages may exceed the system's maximum frequency rating, or reduce the average frequency to such an extent that it affects performance. For these reasons, apportionments between 0.5% and 2.5% are most common.
Spread Spectrum Timing Generation The device generates a frequency modulated clock to increase its occupied bandwidth. By increasing the bandwidth of the fundamental wave and its harmonics, the amplitude of electromagnetic radiation is reduced.
The amplitude of the harmonics of the modulated clock is much lower than that of the unmodulated signal. The reduction in amplitude depends on the harmonic number and frequency deviation or spread. The conversion formula is: db=6.5+9*log10(p)+9×log10(f) where p is the deviation percentage and f is the frequency at which the reduction is measured in MHz.
The output clock is modulated by the waveform. This waveform minimizes the amplitude of radiated electromagnetic emissions, as discussed by Bush, Fessler, and Harding in "Spread Spectrum Clocking for Radiated Emission Reduction." Cypress does offer more spread and greater EMI reduction options.

Application Information Recommended circuit configuration for optimum performance in system applications VDD decoupling is important to reduce both phase jitter and EMI emissions. The 0.1-µF decoupling capacitor should be placed as close as possible to the VDD pin, otherwise the added tracking inductance will cancel its decoupling capability. The 10-µF decoupling capacitors shown should be of the tantalum type. For further EMI protection, a VDD connection can be made through a ferrite bead Recommended Board Layout shows the suggested two-layer board layout.
Recommended circuit configuration notes:
4. The frequency offset (offset) is given relative to the ideal peak value which is the same as the input reference frequency in the case of downward extension for W180-01, -02 and -03 products only.
5. For w180-51, -52 and -53 products, there is no offset (shift) in the center alignment.
C1 = high frequency power supply decoupling capacitor (0.1-µF recommended).
c2 = common supply low frequency decoupling capacitor (10-µf tantalum recommended).
R1 = line impedance match