5 ns for pin logic delay on all pins
fcnt to 100 MHz
36 macrocells, 800 usable gates up to 34 user I/O pins
5 Volt In-System Programmable
10,000 Program/Erase Cycle Endurance Program/Erase Enhanced Pin Lock Structure Flexible 36V18 Function Blocks Over the Full Commercial Voltage and Temperature Range
90 product terms drive any or all of the 18 macrocells within the functional block Global and product terms clock, output enable, set and reset signals Extensive IEEE Standard 1149.1 boundary scan (JTAG) support Programmable Power Reduction Mode Slew Rate Control for Individual Outputs User Programmable Ground Terminal Function Extended Mode Safety Features for Design Protection High Drive 24 mA Output
3.3V or 5V I/O capability Advanced CMOS 5V FastFlash technology supports parallel programming of more than one XC9500 at the same time Offers 44-pin PLCC, 44-pin VQFP, 48-pin CSP packages
The XC9536 is a high-performance CPLD that provides advanced system programming and testing capabilities for general purpose logic integration. It consists of 8 36V18 function blocks, providing 800 usable gates with a propagation delay of 5ns.
Power Management In the XC9536, power consumption can be reduced by configuring the macrocell into standard or low-power operating modes. Turn off unused macrocells to minimize power consumption.
The operating current for each design can be approximated using the following formula for specific operating conditions:
icc(ma)=mchp(1.7)+mclp(0.9)+mc(0.006ma/MHz)f, where:
mchp=macrocell in high performance mode
mclp=macrocells in low power mode mc=total number of macrocells used f=clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.

Figure 1: Typical ICC vs Frequency for XC9536

Figure 2: The XC9536 building block outputs (indicated by black lines) drive the I/O blocks directly.

Equipment Part Marking and Ordering Combination Information Notes:
1. Due to the small size of the chip scale packages, the part markings on these packages do not match the samples above, and the markings cannot contain the full part number. Part marking on chip scale packaging:
Row 1 = X (Xilinx logo) followed by the truncated part number (no XC), which is 95x xx.
Line 2 = Not relevant to device part number.
Row 3 = Not relevant to device part number.
Row 4 = Package code, speed, operating temperature, three digits independent of device part number. Packaging code: C1=CS48.