CD4040 is a 12-bit binary serial counter, all counter bits are master-slave flip-flops. The counter counts on the falling edge of the clock, and when CR is high, the counter is cleared. Due to the use of a Schmitt trigger on the clock input, there are no restrictions on pulse rise and fall times. All inputs and outputs are buffered.

Figure 1 CD4040 pin diagram

Pinout symbol:

10 feet: clock input

11 feet: clear terminal

Q0～Q11: Counter pulse output terminal

VDD: positive power supply

Vss: ground

Recommended working conditions:

Power supply voltage range…………3V～ 15V

Input voltage range…………0V～VDD

Limit value: power supply voltage...－0.5V～18V, input voltage...－0.5V~VDD+0.5V, input current......±10mA, storage stability...－65℃～150 °C

The charging circuit of nickel-cadmium battery composed of CD4040

Figure 2 shows the NiCd battery charger composed of CD4040 counter chip. It can charge four cadmium-nickel batteries with a capacity of 500mA in series, the charging current is 50mA, the charging time is 1.5 hours, and it has the function of automatic power off after charging is completed. The 555 time base circuit constitutes a clock signal generator, which generates a square wave signal of 10Hz with a period of 6 seconds. When the power is turned on, because the ③ pin of IC2 outputs a low level, the semiconductor tube VT1 is turned on, and the relay K1 is pulled in to work, the contact K1-1 is closed, and the switch S is in self-protection. At this point the charging current flows to the battery and starts charging the battery. The status indicator LED is illuminated to indicate that charging is in progress.

Fig. 2 The charging circuit of nickel-cadmium battery composed of CD4040

CD4040 counter constitutes frequency divider and charging circuit. When the power is turned on, the clock signal generated by ICl is output to the ⑩ pin of IC2, and IC2 starts to count. Since IC2 is connected as a frequency divider of 8192 :1, only when the count pulse reaches 8192 will the ③ pin of IC2 change from low level to high level, so that VT1 is turned off, K1 stops working and releases the contact K1-1, making it disconnected, which stops charging. VD2 is used to prevent battery current from flowing back into the circuit.

0～16 Hours Stepless Timing Controller Circuit Principle and Design ( NE555 , CD4040)

As shown in Figure 3, it is a stepless timing control circuit for 0 to 16 hours. The controller consists of a two-stage timer and driver. The timing circuit 1 is composed of IC1 (555) and two 12-bit binary counter/frequency dividers IC2 and IC3 (CD4040), which can generate 0, 1, 2... Among them, the oscillation period of the multivibrator composed of IC1 (555) and W1, R2, and C1 is Tl=0.693 (Rw1+ 2R2 ) C1. The period corresponding to the parameters shown in the figure is about 34 seconds. After the oscillation signal is frequency-divided by IC2 and IC3, the status signals of 8, 4, 2, and 1 hour are obtained at the Q12, Q11, Q10, and Q9 terminals of IC3. By using the combination of switches K2 to K5, 0, 1, and 2 can be obtained. ......14 and 15 hours a total of 16 time signals.

Figure 3 The stepless timing controller circuit

Timing circuit II is composed of IC4 (555) and two 12-bit binary counter/divider IC5 and IC6 (CD4040), which is controlled by timing circuit I, that is, timing circuit I controls the timing by controlling the reset pin ④ of IC4 Timer II, and Timer I can generate a continuously adjustable time signal from 0 to 60 minutes. Among them, the oscillation period of the multivibrator composed of IC4 (555) and R5, W2, and C3 is T=0.693 (2Rw2+R5) C3. Adjusting W2 can make T2 change within the range of 0 to 4290 seconds. After frequency division by IC5 and IC6, the timing range of the Q12 end of IC6 is 0 to 60 minutes.

The total timing time of the controller is: timing I (hours) + timing II (minutes). When the preset timing is reached, the corresponding output Q terminals of IC3 are turned to high level, and Q12 of IC6 is also turned to high level, so that the thyristor SCR is turned on, the relay J is pulled in, and the LED is illuminated. C2 and R3 in the circuit are used for automatic clearing when power on.

Second reference pulse generation circuit

Figure 4 Second reference pulse generation circuit

The 32768 Hz oscillator source of IC1 (CD4060) gets 1/2S pulse at pin 3 (Q14) of the output terminal after 14-level frequency division, and rushes into the two-frequency divider composed of IC2 (CD4040). The second reference pulse is obtained on pin 9 of IC2.