The DF1704 is a high-performance stereo 8x oversampling digital interpolation filter designed for high-end consumer and professional audio applications. The DF1704 supports 24-bit, 96kHz operation and has user-programmable features including selectable filter responses, de-emphasis, attenuation and input/output data formats. The DF1704 is the ideal companion to the Texas Instruments (TI)\x92 PCM1704 24-bit audio digital-to-analog converter. This combination allows the construction of very high performance audio systems and components.

figure 1

System Clock Requirements

The system clock of the DF1704 can be provided by an external clock signal at XTI (pin 6), or through the on-chip crystal oscillator. The system clock rate must be running at 256fS, 384fS, 57fS or 768fS, where fS is the audio sample rate. But it should be noted that the 768fS system clock cannot be used when fS=96kHz. Additionally, the on-chip crystal oscillator is limited to a maximum frequency of 24.576MHz. Table 1 shows typical system clock frequencies for selected sample rates. The DF1704 includes a system clock detection circuit, which determines that the system clock rate is in use. The COM stripping frequency of this circuit is related to the system clock input (XTI) LRCIN input rate to determine the multiplier of the system clock. Ideally, LRCIN and BCKIN should be derived from the system clock to ensure proper synchronization. If the phase difference between the system clock and LRCIN is greater than ±6-bit clock (BCKIN) period, synchronizing the system and LRCIN clocks will be performed automatically by the DF1704 Meiyun. See Figure 1 for the timing requirements for the system clock input.

Table 1

figure 2

RESET The DF1704 also has an internal power-on reset circuit and a reset pin RST (pin 6) for providing an external reset signal. Internal power-on reset is performed automati- when power is applied to the DF1704, as shown in Figure 2. The RST pin can be used to synchronize the DF1704 with a system reset signal, as shown in Figure 3.

During power-on reset ( 1024 system clocks), the DF1704 output is pulled low. When an external forced reset occurs, the output during initialization is forced to a low cycle (1024 system clocks), then a LOW- to high transition on the RST pin occurs afterward, as shown in Figure 3.

Audio input interface The audio input interface consists of BCKIN (pin 2), LRCIN (pin 28) and DIN (pin 1). BCKIN is the input bit clock, which is used to clock the data applied to the input serial interface of the DF1704 at DIN. Input data at DIN is shifted into the DF1704 on the rising edge of BCKIN. The left/right clock, LRCIN, is used as the word line latch for audio input data. BCKIN can run at 32FS, 48fS or 64FS, where fS is the audio sampling frequency. LRCIN operates at FS rate. Fig. 4(a??) shows the input data format through Fig. 4(c), which is SEL-ected by hardware or software control. Figure 5 shows the timing requirements for the audio input interface.

image 3

Figure 4

PCB layout

In order to obtain the specified performance from the DF1704 and its associated D/A converter, proper printed circuit board layout is critical. Figure 6 shows two methods for obtaining the best audio performance. Figure 6(a) shows a standard, mixed-signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The plot should be placed on a split plane that separates the routing and power planes. The DF1704 and all digital circuits should be placed in the digital section, while the audio DAC and analog circuitry should be placed in the analog section of the board. A common connection between digital ground and analog ground is required and is made at a single point as shown. For Figure 6(a), the digital signal should be routed from the DF1704 using short, direct connections to the audio DAC to reduce the amount of radiated high frequency energy. If necessary, series resistors can be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present on these signals. A value of 50Ω and 100Ω is recommended as a starting point, but designers should experiment with resistor values for best results. Figure 6(b) shows an improved method for high perfor- mans, mixed-signal board layout. This method incorporates the digital isolation between the DF1704 and the audio DAC and provides complete isolation between the digital and analog parts of the board. Burr-Brown ISO150 Dual Digital Couplers provide excellent isolation and operate at speeds up to 80Mbps.

Figure 5

Image 6

Power and Bypass

The DF1704 needs to operate from a single +5V power supply. The supply should be bypassed by a 10µF, 0.1µF capacitor in parallel. The capacitor should be placed as close as possible to VDD (pin 22). Aluminum electrolytic or tantalum capacitors are available for 10µF values, while ceramics are available for 0.1µF values.

Figure 7

basic circuit connections

Figures 7 and 8 show the basic circuit connections to the DF1704. Figure 7 shows the connection control for the device mode, while the software is shown in Figure 8 for the connection mode control. Note that C1 and C2 are placed in both figures because they are physically close to the DF1704.

typical application

DF1704 is usually used in high-performance audio equipment, in combination with high-performance audio D/A converters. Figure 9 shows a typical application circuit example using the DF1704, a digital audio receiver, and two PCM1704 24-bit, 96kHz audio DACs.

Figure 8

Figure 9