The EL4340 and EL4342 are fixed unity gain amplifier multiplexers with high slew rate and excellent bandwidth for video switching. These devices have high impedance output states (HIZ) so that the outputs of multiple devices are connected together. A power-down mode (ENABLE) includes shutting down non-essential circuits for power-sensitive applications. The enable pin, when pulled high, sets the EL4340 and EL4342 into standby power mode - consuming only 18mW of power. An additional feature on the EL4340 is a Latch Enable function (LE), which allows the use of a separate logic control common logic bus.

EL4340 block diagram:

EL4343 block diagram:

Application Information

The general EL4340 and EL4342 triple 2:1 and 4:1 multiplex amplifiers are ideal for high performance switcher matrix elements and routers. Key features include: buffered high-impedance analog inputs and excellent AC performance, driving video lines at output loads down to 150Ω. The unity-gain current-feedback output amplifier operates stably into a capacitive load and a bandwidth-optimized load of 5pF in parallel with the same 500Ω. The total output capacitance can be divided between the capacitance of the PCB and an external load.

Ground Connections For best isolation and crosstalk rejection, all GND pins and NIC pins must be connected to the GND plane. Control Signals S0, S1, Enable, LE, HIZ - these are binary coded, TTL/CMOS compatible control inputs. Input selected on S0, S1 pins. All three amplifiers are switched simultaneously from their respective inputs. Enable, LE, and HIZ pins are used to disable sections to save power, the last logic state in the latch and the tri-state output amplifier, respectively. Using termination resistors close to the section for control signal rise and fall times less than 10ns will reduce transient coupling to the output.

HIZ transient response

Electricity Precautions

The ESD protection circuit uses internal diodes for all pins at V+ and V- supplies. In addition, a dV/DT-trigger clamp is connected between the V+ and V- terminals, as shown in the equivalent circuit 1 through the pin description in Section 4 table. The dv/dt trigger clamp applies a maximum supply turn-on slew rate of 1V/µs. Destructive currents can flow power supply rates in excess of 1V/µs - such as during hot plugging. Under these conditions, additional methods should be employed to ensure that the rate of rise is not exceeded. It must be taken into account that the commands in this system are applied to the V+ and V- pins, as well as the analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure Schottky protection circuit) will shunt destructive current away from the internal V+ and V- ESD diode events the V+ supply is applied before the V-supply on the device. If a positive voltage is applied to the logic or analog video input pins before V+ is applied, current will flow through the V+ pin of the internal ESD diode. The large presence of decoupling capacitors and other circuit loading effects connected to V+ can cause destructive current flow through ESD diodes and other active circuit devices. Therefore, proper current limiting is necessary for the digital and analog inputs to prevent damage at the time when the voltage of these inputs is more active than the V+ HIZ state. The internal pull-down resistor ensures that the device will be active on the HIZ pin connected. The HIZ state will be established at about 15ns (Figure HIZ transient response) by going to a logic high (>2V) on the HIZ pin. If the HIZ state is selected the output is connected in parallel with a high impedance of approximately 1.4MΩ taking 1.5pF at a bias current of 10µA from the output. Use this state when more than one multiplexer shares a common output. In the HIZ state the output is tri-stated and keeps its Z high even in the presence of high slew rates. The current supplied during this state is the same active state.

Schottky Protection Circuit

PC board layout

The AC performance of a circuit depends heavily on the attention paid to the design of the printed circuit board. The following are recommendations to achieve the best high frequency performance from your PC board.

Using low inductance components such as chip resistors and chip capacitors is highly recommended.

Minimize the length of signal traces. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, when rounded corners are possible. The hole in the signal line and the inductance should be avoided as much as possible at high frequency. PCB traces greater than 1" start with a rise/fall of a signal showing transmission line characteristics of 1ns or less. High frequency performance can degrade to traces greater than 1" unless stripline is used.

Matching channel and channel analog I/O trace length and layout symmetry. This will minimize transmission delay mismatches.

Maximize the use of AC decoupling PCB layers. All signal I/O lines should be routed on a continuous ground plane (ie no split planes or gaps between these boards). Avoid vias on signal I/O lines.

Use proper value and terminating resistor location. Termination resistors should be placed as close to the device as possible.

When testing use good quality connectors and cables, match the cable type, and keep cable lengths to a minimum.

The recommended minimum of 2 power supply decoupling capacitors (1000pF, 0.01µF) as close to the device as possible - avoids vias between cap and device as vias add unnecessary inductance. The big hat can be farther away. When vias are required for the layout, they should be routed as far from the device as possible.

The NIC pins are placed on either side of the input pins. These pins are not internally connected to the chip. It is recommended to connect these pins to ground to minimize crosstalk.

QFN packages require additional thermal pads for PCB layout rules

The thermal pad is electrically connected to the power supply V- through the high resistance IC substrate. Its main function is to provide a means for dissipating heat in the IC. However, since this is connected to the V- supply through the substrate, the thermal pad must be connected to the V- supply to prevent excess current from flowing to the thermal pad. Do not do this pin to GND, as this may cause large back bias currents to flow between GND and V-. The EL4342 is available in packages with D2=2.48mm and E2=3.4mm pad sizes. Best performance is achieved if the thermal pad is max AC connected to a dedicated decoupling layer in a multi-layer PC board. In cases where dedicated layers are not possible, AC performance may be reduced at upper frequencies. Thermal pad requirements are proportional to power dissipation and ambient temperature. The dedicated layer eliminates the need for a separate thermal pad area. When a dedicated layer is not possible, a 1" x 1" pad area is sufficient for the EL4342 that is fading 0.5W in a +50°C environment. Land area requirements should be evaluated on a case-by-case basis.

EL4340 pin diagram:

EL4343 pin diagram: