Features

The complete interface between LNB and I2C bus

The built-in DC-DC converter used for single 12 V power

operation and high efficiency (typical typical typical (typical example . 93%@0.5 (1)

External optional output current limit

The resistor

Compatible with the output of the main satellite receiver

voltage specification [123 ]

Auxiliary modulation input (EXTM pins)

Promote Diseqc #8482; 1.x encoding

Accurate built -in 22 kHz audio generator set

widely acceptable acceptance Standard

The rear regulator decreases, high efficiency

Integrated power NMOS boost PWM

Allow low power loss

Internal overload and over -temperature

Protection of the diagnostic position with I2C

LNB short -circuit dynamic protection

The ± 4 kV ESD tolerance on the output power supply feet

[

123] The top box satellite receiver

TV satellite receiver

PC card satellite receiver

It is used to simulate and digital satellite receiver, LNBH23L It is a single -chip voltage regulator interface IC. It is assembled in the QFN32 5 X 5 medium to provide the 13/18 V power supply and the 22 kHz audio signal sent to the LNB under the antenna disk Low cost provides a small number of solution components, low power consumption has simple design and I2C standard interface.

Application information

This integrated circuit There is a built-in DC-DC boost converter, from a power supply from 8 V to 15 V to generate a linear rear regulator at the minimum voltage (VUP) 0.55 W typical dispersion power. The rear regulator drop is to keep the interior in Vup-Vout u003d 1.1 V (typical value). The lack of the latter locking circuit will reduce the entire circuit when the VCC is provided to the fixed threshold (usually 6.7V). 123] Note: In this file, VOUT is used as a voltage output (VORX pin) on a linear rear regulator.

Disease Control #8482; Data Code

Internal 22 kHz audio The generator can be repaired according to the standard, and the TTX bit (or TTX pin) canQin) Allows the immediately of illness #8482; data coding, or requires 22 kHz in a continuous mode through 10 I2C bits. In the standby state (EN position low), the TTX function must be disabled and the TTX is set to low. In addition to the internal 22 -kilometer sound generator, the auxiliary modulation pin (EXTM) can be driven by the external 22kHz power supply in this case, and the TTX must be set to low.

Disease Control #8482; 1.X EXTM PIN implementation

In order to improve the flexibility of design and reduce the total application cost Stack to VORX DC output voltage. A proper DC closed -lock capacitor coupling modulation signal must be used to EXTM pins. If the EXTM solution is used, the output R-L filter can be removed (see Figure 5) to save the cost of external components. If this configuration is to keep the TTX set as low. The pins EXTM adjust the VORX voltage by connecting the coupling capacitor in series, so that: VORX (AC) u003d VEXTM (AC) x GEXTM, where VORX (AC) and VEXTM (AC) are VORX and EXTM pins, and GEXTM is from EXTM to VORX. Voltage gain.

Disease Control #8482; 1.x use VOTX and EXTM PIN to implement connection. If the external 22 kHz audio source is unavailable, you can use the internal 22 kHz audio generator signal Essence The VOTX pin must prevent the internal circuit prevention by setting the TTX function as a high level. This may be controlled through the TTX pin or I2C bit. In this way, the VOTX 22 kHz signal will be superimposed to VORX DC voltage to generate LNB output 22 kHz tone (see Figure 3). After setting the TTX to high, you can activate Voten by sending PIN or DS22 during the sending process. The DSQIN internal circuit activated the 22 kHz tone on the VOTX output 22 kHz tone from the TTL signal on the DSQIN pin to 25 μs delay, and stopped the μS delay after the expiration of the TTL signal at a period ± 25. Once the audio transmission expires, the TTX must be disabled in the VOTX internal circuit by setting the TTX to low. 13/18 Volume power supply has always been powered from VORX's feet to LNB.

PDC optional circuit used for DISEQC #8482; 1.x applications use

VOTX signal to EXTM pins in some applications, in low output current ( lt ( lt ; 50 mAh) When there is a large LNB output capacitor load under, 22 kHz's tone may be distorted. In this case, the external components shown in the typical application circuit (see Figure 4) that can be connected to the ""optional"" connection can be added in VORSell u200bu200bbetween X and PDC. This optional circuit is used as active drop -to -be -off. The capacitor is exported only when the internal 22 kHz tone is activated. This optional circuit is not needed in the standard application of iOut GT; 50 mA and capacitor loads up to 250 nf.

I2C interface

The main function of IC is controlled by the I2C bus, and 6 -bit registers are written on the system (SR 8 bits are in the writing mode). There are 5 digits on the same register that can be read back (SR 8 digits in the read mode) to provide the function (OTF, OLF) and three output voltage register status (EN, VSEl , LLC) IC (see the diagnostic function part below). In the reading mode, there are 3 testing positions (test 1-2-3) MCU must ignore this. In the writing mode, two testing positions (test 4-5) must always lower.

Output voltage selection

When the IC part is in the standby mode (EN is low), the power block is disabled. When the regulator block is activated (EN is high), the output logical control is 13 or 18 V, and the VSEL bit (voltage selection). In addition, LNBH23L also provides LLC I2C bits, which can increase the selected voltage value to compensate for the voltage drop along the output line. LNBH23L also meets the US LNB power supply standards. In the standby state (EN low), all I2C and TTX pins must be set to low (if the TTX pin is not used, it can keep floating or ground, but the TTX bit must be set to low in the standby state).

Diagnosis and protection function

LNBH23L has two diagnostic internal functions, read 2 ON system registers through the I2C bus (SR position in the reading mode). The diagnostic position is in a normal working state (whether the failure is detected) and the settings are low. The diagnostic position is dedicated to overheating and overload protection status (OTF and OLF).

Over -current and short -circuit protection and diagnosis

In order to reduce the total power consumption of overload or short circuit, the device has dynamic short circuit protection. You can set the short -circuit circuit current to protect the static (simple current clamp) or dynamically via PCL

I2C SR. When the PCL (pulse current limit) bit is set to low, the dynamic work of over-current protection circuit: Once the overload is detected, the output is closed-closed for a period of time, usually 900 milliseconds. At the same time, the system register is set to ""1"". After this period of time, the output will restore Ton u003d 1/10 TOFF u003d 90 milliseconds (typical value). At the end of the ton, if the overload is still detected, the protective circuit will cycle through TOFF and TON again. The overload was detected at the final tons, the normal operation was restored, and the OLF diagnostic level was reset to a low. The typical TON+TOFF time is 990ms, which is calculated from the insideThe timer is determined. This dynamic operation can greatly reduce power consumption in short circuits, and can still ensure that in most cases. However, when the output may cause the launch difficulties in the high -capacity load, it is dynamically selected. This can be solved by starting any power under the static mode (PCL) to solve u003d 1), and then switch to the dynamic mode (PCL u003d 0) after the selected time depends on the output capacitor. In the static mode, the diagnosis of the OLF bit is ""1"" when the OLF bit is transferred to the current clamping limit, and the low level becomes clear under the overload conditions.

Thermal protection and diagnosis

LNBH23L can also prevent overheating: when the knot temperature exceeds 150 ° C (typical value), the boost converter and linear regulator are closed, and the OTF SR position settings are diagnosed. For ""1"". Return to normal operation, the OTF position is reset to the knots to cool to 135 ° C (typical value).

Output stream selection

Linear regulator current limit threshold foot. The resistance value is limited by defining the output current through the following formula: IMAX (a) u003d 10000/RSEL, RSEL is a resistor connected between ISEL and GND. The maximum optional current limit threshold should be 0.65 a typical value, and RSEL u003d 15 kΩ. The above formula defines the threshold.

Note: External components need to meet DISEQC #8482; bus hardware requirements. The entire application is in line with Diseqc #8482; specifications are not used to use this IC. Notice: Diseqc #8482; is the trademark of Eutelsat.

1. The absolute maximum rated value means that the value may be damaged by the value that may be damaged. These are just under pressure levels under these conditions, and the operation of the device is not implicit. Exposure to exposure under absolute maximum rated conditions may affect the reliability of the device. All voltage values u200bu200bare related to network grounding terminals.

2.byp pins are only used to connect external ceramic capacitors. The pin and external current or voltage source may cause permanent damage to the device.

I2C bus interface Data transmission from the main microprocessor to LNBH23L, otherwise The bus interface, including the 2 -line SDA and SCL (the resistor with a pull -up polar power supply voltage must be connected external).

Data validity

As shown in Figure 6, data on the SDA line must stabilize the clock in the first half of the period. The level of the data cable can only be low on the clock SCL line signal.

Starting conditions

As shown in Figure 7, the starting condition is the high to low conversion of the SDA cable, and SCL is high. The stop condition is the low to high conversion of the SDA line, while the SCL is high. The stop condition must be sent before each startup condition.

byte format

Each byte transmitted to the SDA must contain 8 bits. Each byte must be confirmed behind. First transmit MSB.

Confirm

Master (microprocessor) confirming the clock pulse (see Figure 8). The confirmed peripheral device (LNBH23L) has a drop -down (low) SDA cable during the confirmation clock pulse, which makes the SDA line stable during this clock pulse. The addressing peripheral device must be generated after receiving each byte, otherwise the SDA line will be kept at a high level in the ninth clock pulse time. In this case, the main transmitter can stop information transmission to stop transmission. LNBH23L does not generate confirm whether the VCC power supply is lower than the lack of voltage locking threshold (6.7 V typical value).

Unconfirmed transmission

Avoid testing the confirmation of LNBH23L, microprocessors can use the simpler one to wait for one clock without checking its transmission and sending new data. Of course, this method is not easy to be protected by error reduction.

Diagnosis Receiving data (I2C read mode)

lnbh23L to MCU to MCU The host provides a copy of the diagnostic system register, obtains information through the I2C bus under the reading mode. By send a chip address set to 1 by R/W bit. At the clock generated by the following host, LNBH23L emits a byte (MSB first transmission) on the SDA data bus. At nine o'clock, the host can:

Confirm the receiving, start to transmit another byte LNBH23L

in this way, stop reading the three -bit of the communication register of the read mode as corresponding writing The copy of the output voltage is read back to the register status (LLC, VSEL, EN), the diagnostic information of the two-bit transmission of overheating (OTF) and output overload (OLF). MCU software ignores. In normal operation, the diagnostic bit is set to zero, and if a failure occurs, the corresponding bit set is 1. All positions were reset to zero when starting.

Electric I2C interface reset

The built -in I2C interface of LNBH23L is automatically reset when power is powered. As long as the VCC is still lower than the underwriting voltage lock (UVL) threshold (6.7 V), the interface does not respond to any I2C command and system register (SR) initialization to a full zero, so the power block is disabled. Once VCC rises to 7.3V. The I2C interface becomes the main microprocessor to configure the main microprocessor and an operable microprocessor. This is due to the lagging provided by 500 millival in the UVL threshold to avoid callingThe reset error re -triggers the circuit.

Address pin

You can select the interface through two address.This pin is compatible with TTL, which can be set according to the address pin feature table 10.

Disease Control #8482; Implement

lnbh23L Pwk modulation of 22kHz carrier by allowing EXTM and VOTX pins.Without this, using LNBH23L only does not mean that the system meets the specifications (see Figure 3, Figure 4, and Figure 5)

Electrical characteristics

Reference typical application circuit, TJ from 0 to 85 ° from 0 to 85 °C, EN u003d 1, vsl u003d lLC u003d TEN u003d PCL u003d Test 4 u003d Test 5 u003d TTX u003d 0, RSEL u003d 15 kΩ, dsqin u003d low, vin u003d 12 v, IOUT u003d 50 mAh, unless there is another instructions.Typical value refer to TJ u003d 25 ° C.VOUT u003d VORX pin voltage.For I2C access to the system register, see the ""Software Instructions"" section.

1.tj 0 to 85 ° C, vi u003d 12 volts

internal use.Do not use this address with other I2C peripheral devices to avoid address conflict.