The DIT4096 is a complete digital audio transmitter suitable for professional and consumer audio applications. SAM-coupling rates up to 96kHz are supported. The DIT4096 COM ply meets the requirements for AES-3, IEC-60958, and EIAJCP1201 interface standards. Figures 1 and 2 show the DIT4096 block diagram when used in software and hardware control modes. The MODE input (pin 28) determines the DIT4096 internal functions used to control the model configuration. In software mode, the serial control port is used to write and read the on-chip control registers and status buffers. In hardware mode, dedicated input pins are provided for configuration and status control. The DIT4096 includes an audio serial port, which is used to interface standard digital audio sources such as analog-to-digital (A/D) converters, digital signal processors (DSPs), and audio decoders. Support left-aligned, right-justified, I 2S data formats are provided. The AES-3 encoder generates multiple streams, continuous Taining audio, status and user data. See Figure 3 for the multiplexed data format. This data is then biphase-mark encoded and output to the differential line driver. The line driver output is connected to the transmission medium, either cable or fiber optic. In the case of twisted pair or coaxial cables, transformers are often used to couple the driver output to the transmission line. This provides both isolation and improved common mode rejection. In the optical transmis-sion, the driver output of TX+ (pin 18) is connected to the optical transmitter module.

figure 1

Reset and Power-Down Surgery

The DIT4096 includes a reset input, RST (pin 15), which is used to force the reset sequence. When the DIT4096 is first powered up, the user must assert RST low in order to begin the reset sequence. The RST input must be low for 500ns of the mini mum. The RST input is then forced high to enable normal operation. For software mode, the reset sequence will force the default settings of all internal registers. Additionally, the reset sequence will force all channel status bits to 0 in software mode. While the RST input is low, the transmitter outputs, TX- (pin 17) and TX+ (pin 18), are forced to ground. When setting RST high, the TX- and TX+ outputs will remain low until the rising edge of the sync clock is detected on pin 12. Once this happens, the TX- and TX+ outputs will become active, driven by the output of the AES-3 encoding device. In software mode, the DIT4096 also includes software reset and shutdown bits, located in control register 02H. The software reset bit, RST, and the software shutdown bit, PDN, are both active high.

figure 2

Audio serial port

The audio serial port is used to connect a 3-wire interface DIT4096 to an audio source, such as an A/D converter or DSP. This port supports sampling frequencies up to 96kHz. Signals for this port include SDATA (pin 13), sync (pin 12), and SCLK (pin 11). The SDATA pin is the serial data input port. The SCLK pin can be an input or an output and is used to synchronize the serial data port. The SYNC pin can be either an input or an output, and provides the frame synchroni-matrix special product clock port. The SYNC pin can also be used as a data latch clock input for channel status, user and validity data in hardware mode, and user data input in software mode.

image 3

BLOCK start input/output

The start is used to indicate the channel status of the start data block, and its start frame 0 is used for the AES-3 data stream. For the DIT4096, the block start signal, BLS (pin 25), can be an input or an output. In software mode, the direction of the BLS is used at BLSM bit 01H in the control register (input by default). In hardware mode, the direction of the BLS is set by the BLSM input (pin 24). If BLSM=0, the BLS pin is an input. If BLSM=1, the BLS pin is an output. For operation in software mode, the block start signal is synchronized to the audio serial port's frame synchronization clock, SYNC (pin 12). When BLS is configured as an input pin, it is sampled on the rising edge of SYNC when the ISYNC bit in Control Register 03H is set to 0, otherwise, the iSync bit is set to 1 when it is sampled on the falling edge of the synchronous edge, if Sampled when BLS is high, then a block start condition is indicated. When BLS is configured as an output with the ISYNC bit set to 0, BLS will be high at every 192 falling edges of SYNC for stereo mode, or every 384 falling edges of SYNC for mono mode. BLS will go low on the following falling edge. If the ISYNC bit is set to 1, then BLS transitions on the rising edge of SYNC. Operation in hardware mode is similar to software mode operation, except that there is only a limited number of data formats available for the audio's serial port. For left and right justified formats, BLS behaves as it would with ISYNC=0. For my software mode 2S data format, BLS behaves as it would with ISYNC=1 for software mode.

Channel Status Data Input

Data input for channel status, determined by the control mode in use. In software mode, the channel status data buffer is accessed through the serial control port. Buffer operation is described in detail in this data sheet section entitled Channel Status Buffer Operation (software mode only). In hardware mode, channel status data entry is accomplished by one of two user-selectable methods.

CSS input

In hardware mode, the CSS input state (pin 1) determines the function of the dedicated channel state input. When CSS=0, copy (pin 2), L (pin 3), audio (pin 22), and EMPH (pin 23) input data bits used to set the associated channel state. The COPY and L inputs are used to set copy protection for consumer operation, or to indicate that the transmitter is operating in professional mode without copy protection. The audio input is used to indicate whether the data being transmitted is PCM audio data, or non-audio data. The EMPH input is used to indicate whether PCM audio data has been pre-emphasized using the 50/15µs standard. When CSS=1, the channel status data is input on the C input (pin 2) in serial fashion. Data is clocked on the rising and falling edges of the SYNC input (pin 12). All channel status data bits can be written in this mode, allowing greater flexibility than previous hardware modes with the case CSS=0.

Figure 4

User and Validity Data Entry

The user data bits in the AES-3 data stream allow a convenient way to transmit user-defined or application spe-cific data to another device containing an AES-3 receiver. The U input (pin 27) is used in software and hardware modes to input user data in a serial fashion. FIG. 5 shows a U input timing chart. Validity data indicating that the sample is error-free audio data, or that the sample is defective and unsuitable for further processing. In software mode, the VAL bit in control register 01H is used to write valid data. In hardware mode, VIN (pin 26) is used to input valid data in serial mode. Please refer to Figure 5V input timing hardware mode. When VAL or V=0, this indicates whether the audio data is valid and suitable for further processing. When VAL or V=1, then the audio sample is defective and should not be used.

Figure 5

Line driver output

The DIT4096 includes a balanced line driver. The line driver outputs TX- (pin 17) and TX+ (pin 18). In software mode, the input to the line driver is either from the turn-on output of the chip's AES-3 encoder, or from an external AES-3 encoder at the RXP source input (pin 9). Input source selection uses bit 01 of the control register BYPASSH (default is the on-chip AES-3 encoder). In hardware mode, the line driver source is always the on-chip AES-3 encoder. The output of the line driver will follow normal operation in AES-3 encoded data sources. During a hardware or software reset, or when the device is in power-down mode, the line driver output will be forced to ground. The output can also be forced to control register 01 at any time in software mode by setting the TXOFF bit to 1.

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