In the functional block diagram of the HIP4020 , the four switches and loads are arranged in an H configuration so that voltages driven from terminals OUTA and OUTB can be cross-switched to change the direction of current flow in the load. This is often referred to as four-quadrant load control. As shown in the block diagram, when switches Q1 and Q4 are conducting or in the ON state, the current flows from VDD through the load of Q1 and then through Q4 to terminal VSSB; where OUTA of the load terminal is at positive potential with respect to OUTB. Switches Q1 and Q4 are operated synchronously by the control logic. When logic switches Q3 and Q2 are controlled to an open or closed state, Q1 and Q4 are turned on. To reverse the current flow to the load, the switch states are reversed, with Q1 and Q4 off and Q2 and Q3 on. Therefore, current then flows from VDD through Q3, the overload, and through Q2 to terminal VSSA and to the load terminal OUTB and then at positive potential with respect to OUTA. Logic and B input controls for the enable inputs of terminals ENA and ENB. The ILF output overcurrent limits the fault flag output and displays the fault status for either output A or B or both. The VDD and VSS are the power supply reference terminals for the A and B control logic power input and output ILF. while VDD is the positive power supply. terminals are internally connected to each bridge driver, the VSSA and VSSB power terminals are separate and independent of VSS and can be more negative than the VSS ground reference. The use of a level shifter gate driver circuit with NMOS (low-side) output stage allows relatively controllable level shifting of the output driver to ground.

block diagram

figure 1

application

The HIP4020 is designed to sense the load current feedback from the source output driver sampling low value resistors to the connections of VDD, VSSA and VSSB (see Figure 1). When the sink or source current or OUTAOUTB exceeds the preset OC (over current) limit value of 550mA typical, the current is held at the limit value. If OT (over temperature), the shutdown protection limit is exceeded, and the temperature detection circuit uses BiMOS to limit the junction temperature to 150 °C typical.

The circuit of Figure 1 shows the full H switch in a small motor-driver. Left (A), Right (B) H-switches are output MOS transistors Q1, Q2, Q3 and Q4 that control logic from A and B to A and B inputs. This circuit is for safely starting, stopping and controlling the direction of rotation of the motor and requires no more than 0.5A supply current. Stop functions include dynamic braking. With the enable input low, MOS transistors Q1 and Q3 are OFF; which cuts off the supply current for OUTA and OUTB. With the brake terminal and the start input high, either Q1 and Q4 or Q3 and Q2 will be driven as the conduction direction input control terminal. A pair of MOS transistor outputs is selected for conduction to be determined by a logic level applied to the directional control; resulting in clockwise (CW) or counterclockwise (CCW) shaft rotation. When the brake terminal is toggled high (while holding the ENABLE input high), both the gates of Q2 and Q4 are driven high. Current flowing through Q2 (from motor terminal OUTA) at the instant of dynamic braking will continue to flow through Q2 to the VSSA and VSSB external connections, and then continue to motor terminal OUTB through diode D4. Therefore, kinetic energy dissipated by the resistive windings of the motor (with the path connected in series) is stored in the system. In reverse rotation, current due to FL through Q4 (from motor terminal OUTB), at the instant of dynamic braking, will continue to overflow through Q4 to VSSB and VSSA tie, and then continue through diode D2 to motor terminal OUTA to dissipate storage as Kinetic energy previously described. Among them, VDD to VSS is the power supply reference for control logic, and the minimum actual supply terminal voltage should be no more than 2.0V for correct logic control. The VSSA and VSSB terminals are separate and independent from VSS and can be referenced more negatively than VSS ground. However, the maximum supply level from VDD to VSSA or VSSB must be no greater than the absolute maximum supply voltage rating. Terminals A1, B1, A2, B2, ENA and ENB are internally connected to guard the CMOS circuitry to protect the gate oxide from damage due to electrostatic discharge. (See Figure 3) The input ENA, ENB, A1, B1, A2, and B2 are all CD74HCT4000 logic interface protection levels converted to TTL or CMOS input logic. These input designs typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge. Proper IC handlers should be followed.

figure 2

image 3