The AD7714 is a complete analog front-end measurement application device for low frequencies. The device accepts a low level signal directly from the transducer and outputs a serial digital word. It uses sigma-delta conversion technology to achieve up to 24 bits without loss of code performance. The application input signal is based on a proprietary programmable gain front end analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed through on-chip control registers, allowing adjustment of filter cutoff and settling times. The device has three differential analog inputs (which can also be configured as five pseudo-differential analog inputs) and a differential reference input. It operates from a single supply (+3 9251 ;V or +5␣V). Therefore, the AD7714 can perform conversions for all signal conditioning systems with up to five channels.

The AD7714 is ideal for use in intelligent, microcontroller or DSP based systems. It has a configurable serial interface for three-wire operation. Gain settings, signal polarity and channel selection can be configured in software using the serial port. The AD7714 offers self-calibration, system calibration and background calibration options and allows the user to read and write on-chip calibration registers.

The CMOS structure ensures extremely low power consumption. The power saving mode reduces standby power consumption to 15␣μW typical. The device is available in a 24-lead, 0.3-inch wide plastic Dual In-Line Package (DIP); 24-lead Small Outline (SOIC) package, 28-lead Shrink Small Outline Package (SSOP), and a24-lead Thin Shrink Small Outline Package (TSSOP).

Product Highlights

1. AD7714Y offers the following features in addition to standard AD7714: wider temperature range, Schmitt trigger on SCLK and DIN, operating voltage as low as 2.7 V, lower power consumption, better linearity and Availability of 24-lead TSSOP packages.

2. The power consumption of AD7714 is less than 500 μA (fCLK IN =1␣MHz) or the total supply current is 1 mA (fCLK IN =2.5␣MHz) It is very suitable for loop powered systems.

3. The programmable gain channel allows the AD7714 to accept input signals directly from strain gages or sensors eliminating a lot of signal conditioning.

4. AD7714 is ideal for microcontroller or DSP processor

Applications with a three-wire serial interface reduce the number of interconnects and reduce the number of optocouplers required in an isolated system. This section contains on-chip registers that allow control of filter cutoff, input gain, channel selection, signal polarity and calibration mode.

5. The part has excellent static performance specifications

Features 24 bits with no missing codes, ±0.0015% accuracy and low rms noise ( 140 nV). The effects of endpoint errors and temperature drift are eliminated by on-chip self-calibration, which eliminates zero-scale and full-scale errors.

PIN configuration diagram

AD7714-5 output noise

Table 1a lists the typical notch and output rms noise and effective resolution of the AD7714-5 at -3␣dB frequencies

fCLK␣IN= 2.4576␣MHz , and Table 1b gives the information of fCLK IN =1␣MHz. The numbers given are bipolar input ranges. These figures are typical with VREF of +2.5␣V and BUFFER = 0, generated at an analog input voltage of 0␣V.

The numbers in parentheses in each table are used to indicate the effective resolution of the part (rounded to the nearest 0.5␣LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/GAIN). When pointed out it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be up to 6.6 times the rms number and the effective resolution numbers based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise as quoted in the table.

The output noise of this part comes from two sources. The first is the implementation of electrical noise modulators for semiconductor devices (device noise). Second, when the analog input signal is converted to the digital domain, quantization noise is added. Device noise is low and largely independent of frequency. Quantization noise starts at even lower levels but rises rapidly with increasing frequency, becoming the dominant noise source. Therefore, lower filter notch settings (about 100 ␣ Hz for fCLK IN = 2.4576 ␣ MHz, and 40 ␣ Hz for fCLK IN = 1 ␣ MHz) tend to favor device noise dominance, while higher notch The wave setting is mostly quantization noise. Changing the filter notch and cutoff frequencies in the quantization noise-dominant region results in a more significant improvement in noise performance than in the region where the device noise dominates, as shown in Table I. Furthermore, quantization noise is added after the PGA, so the effective resolution is largely independent of the gain at higher filter notch frequencies. At the same time, device noise is added in the PGA, so for lower notch frequencies, the effective resolution decreases at high gains. Furthermore, in the region dominated by device noise, the output noise (in μV) is largely independent of the reference voltage, while in the region dominated by quantization noise, the noise is proportional to the reference value. The device can be post-filtered to increase a given output data rate - 3␣dB frequencies can also further reduce output noise.

At lower filter notch settings (fCLK IN = 2.4576␣MHz below 60␣Hz, fCLK IN =1␣MHz below 25␣Hz), the performance without missing code is 24 bits. At higher settings, more codes will be lost before the 1␣kHz notch setting For fCLK␣IN=2.4576␣MHz (400␣Hz for fCLK IN=1␣MHz), no missing codes performance is only guaranteed to be 12 bit level.

AD7714-3 output noise

Table IIa shows the output rms noise and effective resolution for some typical notches and -3␣dB frequencies of the AD7714-3

fCLK␣IN=2.4576␣MHz, and Table IIb gives the information of fCLK IN =1␣MHz. The numbers given are bipolar inputs

VREF is the range of +1.25␣V and BUFFER = 0. These figures are typical values and are generated at an analog input voltage of 0␣V.

The numbers in parentheses in each table represent the effective resolution of the part (rounded to the nearest 0.5␣LSB). efficient

The resolution of the device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/GAIN). It should be noted that it is not calculated using the peak-to-peak output noise number. Peak-to-peak noise figures up to 6.6 times rms

numbers, while the peak-to-peak noise-based effective resolution figures can be 2.5 bits lower than the rms-based effective resolution of the noise quoted in the table.

The output noise of this part comes from two sources. The first is the implementation of electrical noise modulators for semiconductor devices (device noise). Second, when the analog input signal is converted to the digital domain, quantization noise is added. Device noise is low and largely independent of frequency. Quantization noise starts at even lower levels but rises rapidly with increasing frequency, becoming the dominant noise source. Therefore, lower filter notch settings (about 100 ␣ Hz for fCLK IN = 2.4576 ␣ MHz, and 40 ␣ Hz for fCLK IN = 1 ␣ MHz) tend to favor device noise dominance, while higher notch The wave setting is mostly quantization noise. Changing the filter notch and cutoff frequencies in the quantization noise-dominant region results in a more significant improvement in noise performance than in the device noise-dominant region as shown in Table II. Also, quantization noise is added after the PGA, so the effective resolution is largely independent of the gain at the higher filter notch frequencies. At the same time, device noise is added in the PGA, so for lower notch frequencies, the effective resolution suffers a little at high gains. Furthermore, in the region dominated by device noise, the output noise (in μV) is largely independent of the reference voltage, while in the region dominated by quantization noise, the noise is proportional to the reference value. The device can be post-filtered to increase a given output data rate - 3␣dB frequencies can also further reduce output noise. At lower filter notch settings (fCLK IN = 2.4576␣MHz below 60␣Hz, fCLK IN =1␣MHz below 25␣Hz), the performance without missing code is 24 bits. At higher settings, more codes will be lost before the 1␣kHz notch setting For fCLK␣IN=2.4576␣MHz (400␣Hz for fCLK IN=1␣MHz), no missing codes performance is only guaranteed to be 12 bit level.

buffer mode noise

Table III lists the typical output rms noise of the AD7714 and some typical notches and effective resolution at -3␣dB frequencies -

5. fCLK␣IN=2.4576␣MHz, BUFFER = +5V. Table IV gives information for AD7714-3, fCLK IN = 2.4576

MHz and BUFFER = +5␣V. The numbers given are for bipolar input ranges, with a voltage of 0␣V produced by the differential analog input. For the AD7714-5, the VREF voltage is +2.5␣V; for the AD7714, the VREF voltage is +1.25␣V. Parentheses in each table are used to efficiently distinguish parts (rounded to the nearest 0.5 LSB). An effective solution device is defined as the ratio of output rms noise to input full scale (ie, 2 × VREF/GAIN). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be as high as 6.6 times the rms number. The effective resolution numbers based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise quoted in the table.

On-chip registers

The AD7714 contains eight on-chip registers that can be accessed through the device's serial port. The first is the communication register, which controls the channel selection, decides whether the next operation is a read or write operation, and also decides that it registers the next read or write access. All communications with the device must begin with a write to the device. After power-up or reset, the device needs to write to the communication register. Data Written This register determines whether the next operation to the device is a read or write operation, and determines which register this read or write operation takes place. Therefore, a write access to any other register on the device begins with a write to that device after the communication register is written to the selected register. Read operations from any other registers on the device (including

output data register) begins with a write to the communications register, followed by a read of the selected register. The communication register also controls the channel selection, and the DRDY status can also be read to obtain the communication register. The second register is the mode register, which determines the calibration mode and gain settings. The third register, labeled Filter High Register, determines the word length, bipolar/unipolar operation and contains the upper 4 bits of the filter select word. The fourth register, labeled Filter Low Register, contains the lower 8 bits of the filter select word. The fifth register is the test register and can be accessed when testing the device. The sixth register is the output data of the data register access unit. The final register allows access to the device's calibration registers. The zero-scale calibration registers allow access to the zero-scale calibration coefficients for the selected input channel, while the full-scale calibration registers allow access to the full-scale calibration coefficients for the selected input channel. Registers are discussed in more detail in the following sections.

Communication Register (RS2-RS0 = 0,0,0)

The communication register is an 8-bit register from which data can be read or written. All communications with the device must begin with a write to the communications register. The data written to the communication register determines whether the next operation is a read or write operation and in which register the operation occurs. Once a subsequent read or write operation to the selected register is complete, the interface returns to the communication register where it expects the write operation. This is the default state of the interface in which the AD7714 waits for a write to the communication register after power-up or reset. In the event of a loss of interface sequence, the AD7714 returns to this default state if a write operation is performed with DIN high for a sufficient duration (comprising at least 32 serial clock cycles). Table V summarizes the bit assignments for the communications registers.

circuit description

The AD7714 is a sigma-delta A/D converter with on-chip digital filtering for measuring wide dynamic range, high frequency signals such as those in weighing scales, pressure sensors, industrial control or process control applications. It contains a sigma-delta (or charge balance) ADC, a calibrated microcontroller with on-chip static RAM, a clock oscillator, digital filters and bidirectional serial communication port. The device consumes only 500µA of supply current and requires only 10µA in standby mode, making it ideal for battery-powered or loop-powered instruments. The device is available in two versions, the AD7714-5, which is specified for operation from a nominal +5␣V analog supply (AVDD), and the AD7714-3, which is specified for operation from a nominal +3.3␣V analog supply. Both versions can operate from a digital supply (DVDD) voltage of +3.3␣V or +5␣V. The AD7714Y grade part operates from a nominal AVDD of 3 V or 5 V, and can operate from a digital supply of 3 V or 5 V. The device Contains three programmable gain fully differential analog input channels that can be reconfigured to five pseudo differential inputs. All channels have a gain range of 1 to 128, allowing the section to accept unipolar signals between 0 mV to +20␣mV and 0 V to +2.5␣V. In bipolar mode, the part handles normal bipolar signals of ±20 mV and quasi-bipolar signals up to ±2.5 V. +2.5␣V when the reference input voltage is equal to. The reference voltage is +1.25␣V, the input range is from 0 mV to +10 mV to 0 V to +1.25␣V in unipolar mode, in bipolar mode, the device can handle true bipolar signals ±10 mV and quasi-bipolar signals, up to ±1.25 V. This part uses sigma-delta conversion technology to achieve up to 24 bits without missing codes. sigma-delta

The modulator converts the sampled input signal into digital pulses whose duty cycle contains the train of digital information. The programmable gain function on the analog input is also incorporated in this sigma-delta modulator, where the input sampling frequency of the modulator is modified for higher gain. A sinc3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the filter's first notch frequency. This output data can be read from the serial port randomly or periodically up to the output register update rate. The first notch of this digital filter, its -3␣dB frequency and its output rate can be programmed by the filter high and filter low registers. The master clock frequency is 2.4576 MHz,

The first notch frequency and output have a programmable range rate from 4.8 ␣ Hz to 1.01 kHz, giving a programmable range of 1.26 Hz to 265 ␣ Hz for -3 ␣ dB frequencies. The basic connection diagram of the device is shown in the figure below. This means that both the AVDD and DVDD pins of the AD7714 are driven by an analog +3␣V or +5␣V supply. Some applications will use separate supplies to drive AVDD and DVDD. In the figure, the analog inputs of the AD7714 are configured as three fully differential inputs. The section is set

Unbuffered mode for these analog inputs. An AD780, precision +2.5 V reference, provides the reference source section. On the digital side, the part is configured for operation with a three-wire CS connected to DGND. A quartz crystal or ceramic resonator provides the main clock source for the device. It is possible that a capacitor on the crystal or resonator must be connected to ensure that it does not oscillate in the overtones of its underlying operating frequency. The value of the capacitor will vary according to the manufacturer's specifications.

analog input

Analog input range

The AD7714 contains six analog input pins (labeled AIN1 to AIN6) that can be configured as three fully differential input channels or five pseudo-differential input channels. The CH0, CH1, and CH2 configuration of the bit communication registers The analog input arrangement and channel selection are as previously outlined in Table VII. Input pairs (differential or pseudo-differential) provide programmable gain inputs that can handle unipolar or bipolar input channel signals. It should be noted that bipolar input signals are referenced to the corresponding AIN (-) inputs of the input pair. In unbuffered mode, the common-mode range of these inputs is from AGND to AVDD providing the absolute value of the analog input voltage between AGND␣-␣30␣mV and AVDD +30␣mV. This means that in unbuffered mode, the part can handle both

Unipolar and bipolar input ranges for all gains. In buffered mode, the analog input can handle larger source impedance, but the absolute input voltage range is limited from AGND␣+50␣mV to AVDD - 1.5␣V, which is also the limit of the modulo range. This means that buffer mode has some limitations on the allowable gain for bipolar input ranges. Care must be taken when setting the common mode voltage and input voltage range so that the upper limit is not exceeded, otherwise the linearity performance will be degraded. In unbuffered mode, the analog input goes directly to

7␣pF input sampling capacitor, CSAMP. The DC input leakage current in this unbuffered mode is a maximum of 1␣nA. The result is that the analog input sees a dynamic load at the input sample rate (see Figure 3). This sample rate depends on the master clock frequency and the selected gain. CSAMP is charged to AIN(+) and discharged to AIN(-) every input sampling period. The effective on-resistance RSW of the switch is usually 7␣kΩ.

Unbuffered Analog Input Block Diagram