feature
8226 ; optional watchdog timer Low VCC detection and reset assertion - Four standard reset threshold voltages - Adjust low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC=1V Low power CMOS -<20µA maximum standby current, watchdog on -<1µA standby current, watchdog off -3ma active current Input cycle time (typical) Built-in accidental write protection - power up/down protection circuit - protects 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable block lock? Protection • 400kHz 2-wire interface • 2.7V to 5.5 V supply operation • Components available
-8 liter SOIC-8 liter TSSOP
• Lead Free + Annealed (RoHS Compliant)
Block Diagram Description

X4283 , X4285 in: power-on reset control, watchdog timer, supply voltage monitoring and block lock to protect serial EEPROM memory. This combination reduces system cost, reduces board space requirements, and improves reliability.
Applying power to the device activates the power supply.
A reset circuit that keeps reset/reset active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.
The watchdog timer provides an independent protection mechanism for the microcontroller. When the microcontroller fails to restart the timer within a selectable timeout interval, the device will activate a reset/reset signal. The user selects the interval from three preset values. Once selected, the interval does not change even after cycling the power.
The device's low voltage detection circuit protects the user's system from low voltage conditions, resetting the system trip point when VCC falls below the set minimum VCC. reset/reset is asserted until V returns to the proper operating level and stabilizes. Four industry standard vtrip thresholds are available, however, intersil's unique circuitry allows the thresholds to be reprogrammed to meet custom requirements, or fine-tuned for applications requiring higher accuracy

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC handling procedures

Operation principle Power-on reset Power on X4283 and X4285 activates the start-up reset circuit, and activates the reset/reset pin. This signal provides several benefits.
– Prevents the system microprocessor from starting work under low voltage conditions.
– It prevents the processor from working until the oscillator is stable.
– It allows the FPGA to download its configuration before the circuit is initialized.
– It prevents communication with the EEPROM, greatly reducing the possibility of data corruption at power up.
The circuit releases when V exceeds the device V threshold for 200 ms (nominal). Cocos Islands Travel Reset/Reset allows the system to start running.
Low Voltage Monitoring During operation, the x4283, x4285 monitor the V cocos level and assert a reset/reset if the supply voltage falls below a preset minimum V. The reset/reset signal prevents the microprocessor from operating in a power-down or power-down state. The reset/reset signal remains active until the voltage drops below 1V. It also remains active until V returns and exceeds V for 200 ms. Travel Cocos Travel Watchdog Timer The watchdog timer circuit monitors the activity of the microprocessor by monitoring the sda and scl pins. The microprocessor must periodically toggle the sda pin high to low while the scl high (which is a start bit) will prevent the reset/reset signal until the watchdog timeout period expires. The state of two nonvolatile control bits in the status register determines the watchdog timer period. The microprocessor could change these watchdog bits, or they could be "locked out" by tying the WP pin.
Accidental EEPROM Write Protection When reset/reset becomes active due to a low voltage condition or watchdog timer timeout, any ongoing communication will be terminated. While reset/reset is active, no new communication is allowed, nor can non-volatile write operations be initiated.
While reset/reset is active, non-volatile writes in progress can complete.
Additional protection mechanisms provide memory block lock and write protect (wp) pins. These are discussed elsewhere in this document.
V-threshold reset routine cocos set vtrip level sequence (vcc = desired vtrip value and bit settings)
X4283 and X4285 are shipped with standard vThreshold (V) voltage. This value does not change under normal operating and storage conditions. However, in applications where the standard V is not exactly correct, or if the V value requires more precision, the X4283, X4285 thresholds can be adjusted. The procedure is described below and uses the application of non-volatile control signals. Cocos Islands Travel Travel Travel Set V Voltage Travel This step is used to set V to a higher or lower voltage value. Before setting a new value, the trigger point must be reset. To set a new V voltage, first set the WEL bit in the control register, then apply the desired vthreshold voltage to the V pin, apply the programming voltage V to the wp pin and 2 bytes of address and 1 byte of "00" data . A stop bit after a valid write operation initiates the V programming sequence. Bring wplow to complete the operation. Travel Travel Cocos Ph Travel Reset V Voltage Travel This step is used to set V to the "native" voltage level. For example, if the current V is 4.4V and the new V must be 4.0V, then V must be reset. When V resets, the new V value is less than 1.7V. This step must be used to set the voltage to a lower value. travel travel travel travel travel travel travel reset vtrip level sequence (vcc>3v.wp=12-15v, WEL bit setting)
Example of a vtrip reset circuit To reset a new V voltage start by setting the WEL bit in the control register, apply V and the programming voltage V to the wp pin and 2 bytes of address and 1 byte of "00" data. A stop bit for a valid write operation initiates the V programming sequence. Bring wplow to complete the operation. The travel cocos phosphorus travel control register provides a mechanism for the user to change block lock and watchdog timer settings. The block lock and watchdog timer bits are non-volatile and do not change when powered down.
The control register is accessed at address ffff. It can only be modified by performing a byte write operation directly to the register address, and only one data byte is allowed per register write operation. Before writing to the control register, the WEL and RWEL bits must be set using a two-step process, and the entire sequence requires 3 steps.

Register Write Enable Latch (Volatile)
The RWEL bit must be set to 1 before writing to the control register
WEL: Write Enable Latch (volatile)
The WEL bit controls access to memory and registers during write operations. This bit is a volatile latch that powers up in the low (disabled) state. When the WEL bit is low, writes to any address, including any control registers, are ignored (no acknowledgment is issued after the data byte). The WEL bit is set by writing a '1' to the WEL bit and a 0 to the other bits of the control register. Once set, WEL will remain set until it is reset to 0 (by writing '0' to the WEL bit and zeros to the other bits of the control register), or until the part is powered up again. A write to the WEL bit does not cause a nonvolatile write cycle, so the device is immediately ready for the next operation after the stop state.
BP2, BP1, BP0: Block Protection Bits (non-volatile)
The block protection bits bp2, bp1, and bp0 determine which blocks in the array are write-protected. Writes to protected memory blocks are ignored. The block protection bit will prevent writes to one of the eight segments of the array.

Writing to the control register changes any non-volatile bit of the control register requires the following steps:
– Write 02h to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after writing. (operations that start with start and end with stop).
– Write 06h to the control register to set the register write enable latch (RWEL) and WEL bits. It's also an unstable cycle. Zeros in data bytes are required. (operations that start with start and end with stop).
– Write the control register to the value with all control bits set to the desired state. This can be represented in binary as 0xys t 01r, where xy are the wd bits and rst are the bp bits. (operations that start with start and end with stop). Since this is a non-volatile write cycle, it takes 10ms to complete. The RWEL bit is reset by this cycle, and the sequence must be repeated to change the nonvolatile bits.
one more time. If bit 2 is set to '1' in the third step (0xys t11r), the RWEL bit is set, but the WD1, WD0, BP2, BP1, and BP0 bits remain unchanged. Writing the second byte to the control register is not allowed. Doing so aborts the write operation and returns a nack.
– A read operation that occurs between any previous operations does not interrupt a register write operation.
Valid data change on the SDA bus – The RWEL bit cannot be reset without writing the RWEL bit to a non-volatile control bit in the control register, rebooting the device, or attempting to write to a write-protected block.
For example, a device write sequence consisting of [02H, 06H, 02H] will reset all nonvolatile bits in the control register to 0. The sequence of [02H, 06H, 06H] will keep the non-volatile bits unchanged and the RWEL bit set.
Serial Interface Serial Interface Conventions This device supports a bidirectional bus-oriented protocol. The protocol defines any device that sends data to the bus as a transmitter and the receiving device as a receiver. The device that controls the transfer is called the master device, and the device that is being controlled is called the slave device. The host always initiates data transfers and provides clocks for transmit and receive operations. Therefore, devices in this family operate as slave devices in all applications.
Serial Clock and Data
The data state on the SDA line can only change when SCL is low. SDA state changes while SCL is high are reserved to indicate start and stop conditions.
Serial Start Condition All commands are preceded by a start condition, which is a high-to-low transition of SDA when SCL is high. The device continuously monitors the sda and scl lines for a start condition and will not respond to any commands until that condition is met for a serial stop condition

STOP AND WRITE MODES A STOP condition that terminates a write operation must be sent by the host after sending at least 1 complete data byte followed by an ACK signal. If a stop is issued in the middle of a data byte or before sending 1 complete data byte plus its associated ACK, the device will reset itself without performing a write operation. The contents of the array are not affected.
Acknowledgment polling disables the input in a nonvolatile cycle that can take advantage of a typical 5ms write cycle time. Once a stop condition is issued to indicate the end of the host byte load operation, the device starts an internal nonvolatile loop. Confirm that polling can start immediately. To do this, the master issues a start condition followed by a slave address byte for a write or read operation. An ACK will not be returned if the device is still busy in a non-volatile loop. If the device has completed the write operation, an ACK is returned, and the host can proceed with the read or write operation.