The CDCE906 is one of the smallest and most powerful clock synthesizer/jitter cleaner products. Programmable Output Switch Matrix [6x6] Despite its small physical size, the CDCE906 includes a 7-bit postscaler per output. Flexible . It has the ability to generate almost differential input clock or single crystal. The reduced system EMISMBus data interface controller.

To achieve independent output frequencies, the reference divider M and the feedback divider N for each PLL can be set to a value from 1 to 511 for the M divider and 1 to 4095 for the N divider . The PLL-VCO (Voltage Controlled Oscillator) frequency ratio is routed to any one of the six outputs of the freely programmable output switch matrix. The switch matrix includes an additional 7-bit postscaler (1 to 127 ) and an inverting logic for each output. A deep M/N divider ratio allows zero ppm clock generation from any reference input frequency (eg, a27 MHz).

The CDCE906 includes three PLLs that support SSC (Spread Spectrum Clocking). PLL1, PLL2 and PLL3 are designed for frequencies up to 167 MHz and are optimized for zero ppm applications with wide dividers.

PLL2 also supports Center Spread and Down Spread Clocking (SSC). This is a common technique to reduce electromagnetic interference. Additionally, Slew Rate Controlled (SRC) output edges minimize EMI noise. Based on the PLL frequency and divider settings, the internal loop filter components are automatically adjusted for high PLL stability and optimized jitter transfer characteristics. The device supports non-volatile EEPROM programming for easy custom application. It is pre-programmed with a factory default configuration (see Figure 13) and can be reprogrammed to other applications prior to entering the PCB or through in-system programming. Different device settings are programmed via the serial SMBus interface.

Two programmable inputs S0 and S1 can be used to control the most demanding logic control settings in each application (output disable low, output 3-state, power down, PLL bypass, etc.).

CDCE906 has three power pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3 V supply. VCCOUT1 and VCCOUT2 are the output power pins.

VCCOUT1 powers outputs Y0 and Y1, and VCCOUT2 powers outputs Y2, Y3, Y4 and Y5. The two output supply voltages are 2.3 V to 3.6 V. The output drive current is limited at output voltages below 3.3 V.

The operating temperature range of the CDCE906 is 0°C to 70°C.

Terminal allocation diagram

feature

High-performance 3:6 PLL-based clock synthesizer/multiplier/divider

User programmable PLL frequency

No need to program EEPROM programming

Easy online programming via SMBus data

Wide PLL divide ratio allows 0 ppm output clock error

Generate accurate video (27 MHz or 54 MHz) and multiple audio system clock sampling frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)

Clock input accepts crystal or single-ended LVCMOS or differential input signals

Accepts crystal frequencies from 8 MHz up to 4 MHz

Accepts LVCMOS or differential input frequencies up to 167 MHz

Two programmable control inputs [S0/S1, A0/A1] for user-defined control signals

Six LVCMOS outputs with output frequency up to 167 MHz

LVCMOS outputs can be programmed as complementary signals

Selectable output frequency Programmable output switch matrix [6x6] despite small physical size

Low period jitter (60 ps typical)

Functional Spread Spectrum Clocking (SSC)

Programmable Center Extended SSC Modulation

Functional block diagram

Output Switch Matrix Diagram

Application Information

To enhance the flexibility and functionality of the clock synthesizer, a dual-signal serial interface is provided. It follows version 2.0 of the SMBus specification, which is based on the principle of operation of I.

With SMBus, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the SMBus data interface are initialized to their default settings on power-up, so using this interface is optional. Changes to the clock register registers are usually made during system initialization, if needed. The clock driver serial protocol accepts byte write, byte read, block write and block read operation controllers.

For block write/read operations, bytes must be accessed in order from least to most significant (most significant bit first) with the ability to stop after a complete byte has been transferred. For byte write and byte read operations, the system controller can access individually addressed bytes. Once a byte is sent, it will be written to the internal registers and take effect immediately. With the rising edge of the ACK bit, this applies to every byte transferred, whether it's a byte write or block write sequence.

If an EEPROM write cycle is initiated, the data from the internal SMBus registers will be written to the EEPROM. During an EEPROM write, data is not allowed to be sent over the SMBus to the device until the sequence completes. However, data can be read out during a programming sequence (byte read or block read). The programming status can be monitored by EEPIP, byte 24 bit 7.

The diagram below shows how the CDCE906 clock synthesizer is connected to the SMBus. Note that the current through the pull-up resistor (Rp) must meet the SMBus specification (100 μA minimum, 350 μA maximum). If the CDCE906 is not connected to SMBus, the SDATA and SCLK inputs must be connected with 10kΩ pull-up resistors to VCC to avoid floating input conditions.

SMBus hardware interface

Typical applications for the CDCE906 are digital HDTV systems, game consoles, DVD players, DVD plug-in cards for multimedia PCs and desktops.

CDCE906 system application block diagram

Clock Inputs (CLK_IN0 and CLK_IN1)

The CDCE906 has two clock inputs that can be used as:

Crystal oscillator input (default setting)

Two independent single-ended LVCMOS inputs

Differential signal input

The dedicated clock input can be selected by the input signal source Bit[7:6] of byte 11.

Crystal oscillator input

The input frequency range in crystal mode is 8 MHz to 54 MHz. The CDCE906 uses a Pierce-type oscillator circuit that includes an inverting amplifier feedback resistor. However, the user must add external capacitors CX0, CX1) to match the input load capacitance of the crystal (see diagram below). The desired value can be calculated:

CX0 = CX1 = 2×CL-CICB,

Where CL is the crystal load capacitance specified by the crystal unit, and CICB is the input capacitance of the transistor device including the board capacitance (stray capacitance of the PCB).

For example, for a basic 27 MHz crystal with a CL of 9 pF and a CICB of 4 pF,

CX0 = CX1 = (2 x 9pF) - 3pF = 15pF.

It is important to use short PCB traces from the device to the crystal unit to keep the stray capacitance of the transistor oscillator loop to a minimum.