Reset control, watchdog timer and supply voltage monitoring. This combination reduces system cost, reduces board space requirements, and improves reliability.
Applying power to the device activates a power-on reset.
Circuits that keep reset/reset active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.
The watchdog timer provides an independent protection mechanism for the microcontroller. When the microcontroller fails to restart the timer within a selectable timeout interval,
The device activates the reset/reset signal. The user selects the interval from three preset values. Once selected, the interval does not change even after cycling the power.
The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trigger point.
reset/reset is asserted until VCC returns to the proper operating level and stabilizes. Five industry-standard vtrip thresholds are available; however, intersil's unique circuitry allows the thresholds to be reprogrammed to meet custom requirements, or fine-tuned for applications requiring higher accuracy.
Selectable watchdog timer - select 200ms , 600ms , 1.4s, off low VCC detection and reset assertion
- Five standard reset threshold voltages, rated at 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
- Adjust low VCC reset threshold voltage using special programming sequence
- The reset signal is valid until VCC=1V
Low power CMOS
- 12µA typical standby current with watchdog on
- 800NA typical standby current watchdog off
- 3ma active current
400kHz I2c interface
1.8V to 5.5V Power Supply Operation Available in Software Packages
- 8 LD SOICs
- 8 LD MSOPs
Lead-free available (RoHS compliant)
pin
X4003 , X4005 (8 LD SOIC, MSOP) top view
*Reset works on X4003 Reset works on X4005

Power-on reset Power on the X4003/X4005 activates the reset circuit that activates the reset/reset pin. This signal provides several benefits:
8226 ; Prevents the system microprocessor from starting work under low voltage conditions.
• It prevents the processor from operating until the oscillator is stable.
• It allows the FPGA to download its configuration prior to circuit initialization.
When VCC exceeds the device vtrip threshold for 200ms (normal) the circuit releases the reset/reset, allowing the system to begin operation.
During low voltage monitoring operation, the X4003/X4005 monitors the VCC level.
A reset/reset is asserted if the supply voltage is below the preset minimum VTRIP. The reset/reset signal prevents the microprocessor from operating in a power-down or power-down state. The reset/reset signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP by 200ms.
Watchdog Timer The watchdog timer circuit monitors the activity of the microprocessor by monitoring the sda and scl pins. The microprocessor must periodically toggle the sda pin from high to low and scl from high to low as well (this is a start bit) and then a stop condition occurs before the watchdog timeout period expires to prevent a reset /reset signal. The state of two nonvolatile control bits in the control register determines the watchdog timer period. The microprocessor could change these watchdog bits, or they could be "locked out" by tying the WP pin.
watchdog restart
V Threshold Reset Procedure Cocos Islands
The X4003/X4005 are shipped with a standard VCC threshold (VTRIP) voltage. This value does not change under normal operating and storage conditions. However, in applications where the standard vtrips are not quite correct, or if the vtrip values require more precision, the x4003/x4005 thresholds can be adjusted. The procedure is described below and uses the application of non-volatile control signals.
Set V trip This step is used to set vtrip to a higher voltage value. For example, if the current vtrip is 4.4V and the new vtrip is 4.6V, this process will directly make the change. If the new setting is lower than the current setting, the trigger point needs to be reset before setting the new value.
To set a new vtrip voltage, apply the desired vtrip threshold voltage to the VCC pin and connect the wp pin to the programming voltage vp. Then write data 00HTO address 01H. A stop bit after a valid write operation initiates the vtrip programming sequence. Turn WP down to finish.

RESET V VOLTAGE TRIP This procedure is used to set the vtrip to the "native" voltage level. For example, if the current vtrip is 4.4V and the new
The vtrip must be 4.0V, then the vtrip must be reset. When resetting the vtrip, the new vtrip is less than 1.7V. This step must be used to set the voltage to a lower value.
To reset the new vtrip voltage, apply the desired vtrip threshold voltage to the VCC pin and tie the wp pin to the programming voltage vp. Then write 00H to address 03H. The stop bit for a valid write operation initiates the vtrip programming sequence. Turn WP down to finish.

Control Register The Control Register provides the user with a mechanism to change the watchdog timer settings. The watchdog timer bits are nonvolatile and do not change when powered down.
The control register is accessed via a special preamble in the slave byte ( 1011 ), located at address 1fh. It can only be modified by performing a control register write operation. Only one data byte is allowed per register write operation. Before writing to the control register, the WEL and RWEL bits must be set using a two-step process, and the entire sequence requires 3 steps. See "Writing to the Control Register" on page 7.
The user must issue a stop after sending the control byte to the register to initiate a non-volatile loop storing WD1 and WD0. After the first byte is entered, the X4003/X4005 will not acknowledge any data bytes written.
The state of the control registers can be read at any time by performing a serial read operation. Each register read operation only reads one byte. After reading the first byte, the x4003/x4005 resets itself. The host shall provide a stop condition consistent with the bus protocol, but a stop is not required to end this operation.
Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" before writing to the control register
WEL: Write Enable Latch (volatile)
The WEL bit controls access to the control register during write operations. This bit is a volatile latch that powers up in the low (disabled) state. When the WEL bit is low, writes to the control register are ignored (no acknowledgment is issued after the data byte). The WEL bit is set by writing a '1' to the WEL bit and a 0 to the other bits of the control register. Once set, WEL will remain set until it is reset to 0 (by writing '0' to the WEL bit and zeros to the other bits of the control register), or until the part is powered up again. A write to the WEL bit does not cause a nonvolatile write cycle, so the device is immediately ready for the next operation after the stop state.

Changing any non-volatile bit of the control register requires the following steps:
• Write 02h to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after writing. (The operation starts and then stops.)
• Write 06h to the control register to set the register write enable latch (RWEL) and the WEL bit. It's also an unstable cycle. Zeros in data bytes are required. (The operation starts and then stops.)
• Write the control register with all control bits set to the desired state. This can be represented in binary as 0xY0 0010, where xy are the wd bits. (The operation starts with a start and ends with a stop.) Since this is a non-volatile write cycle, it takes 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the non-volatile bit again. If bit 2 is set to '1' in the third step (0xy0 0110), the RWEL bit is set, but the WD1 and WD0 bits are left unchanged. Writing the second byte to the control register is not allowed. Doing so aborts the write operation and returns a nack.
• Any reads that occur between previous operations do not interrupt register writes.
• The RWEL bit cannot be reset without writing the RWEL bit to the nonvolatile control bits in the control register, rebooting the device, or attempting to write to a write-protected block.
For example, a device write sequence consisting of [02H, 06H, 02H] will reset all nonvolatile bits in the control register to 0. The sequence of [02H, 06H, 06H] will keep the non-volatile bits unchanged and the RWEL bit set.
Serial interface conventions The device supports a bidirectional bus-oriented protocol. The protocol defines any device that sends data to the bus as a transmitter and the receiving device as a receiver. The device that controls the transfer is called the master device, and the device that is being controlled is called the slave device. The host always initiates data transfers and provides clocks for transmit and receive operations. Therefore, devices in this family operate as slave devices in all applications.
Serial Clock and Data
The data state on the SDA line can only change when SCL is low. SDA state changes while SCL is high are reserved for indicating start and stop conditions

The serial start condition sda line low confirms that it received 8 bits and all commands are preceded by a start condition, which is a high-to-low transition of SDA when SCL is high. The device continuously monitors the sda and scl lines for a start condition and will not respond to any commands until that condition is met.
All communications must be terminated by a STOP condition, which is a low-to-high transition of SDA when SCL is high. A STOP condition is also used to put the device into standby power mode after a read sequence. A stop condition can only be issued after the transmitter has released the bus.
Serial acknowledgment acknowledgment is a software convention used to indicate a successful data transfer. The transmitting device, whether master or slave, releases the bus after transferring 8 bits. During the ninth clock cycle, the receiver will pull out the OF data.
After confirming the start condition and the correct contents of the slave address byte, the device will respond with an acknowledgement. The x4003/4005 also provides an acknowledgment bit for serial writes to the slave address byte after the control register address byte has been correctly received, the byte written to the control register has been received, and the second slave address in question has been read After the Start condition, the master must output the slave address byte. This byte consists of several parts:
• The device type identifier is always "1011".
• Two "0"s.
• One bit from the command byte is the R/W bit. The r/w bits of the slave address byte define the operation to be performed. When the R/W bit is 1, a read operation is selected. Zero-select write operations.
• After loading the entire slave address byte from the SDA bus, the device compares the incoming slave byte data with the correct slave byte. After a proper comparison, the device outputs an acknowledgment on the sda line. Writing to the Control Register To write to the control register, the device needs a slave address byte and a byte address. This gives the master server access to the registers. After receiving the address byte, the device responds with an acknowledgment and waits for data. After receiving 8 bits of the data byte, the device responds again with an acknowledgment. The host then terminates the transfer by generating a stop condition, at which point the device begins an internal write cycle to the non-volatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. If wp is high, the control register cannot be changed. A write to the control register will suppress the acknowledge bit and any data in the control register will not be changed. With wp low, writing to the second byte of the control register terminates the operation and no write occurs.
STOP AND WRITE MODES A STOP condition that terminates a write operation must be sent by the host after sending 1 complete data byte followed by an ACK signal. If a stop is issued in the middle of a data byte or before sending 1 complete data byte plus its associated ACK, the device will reset itself without performing a write operation.
Serial Read Operation A read operation allows the master to access the control register slave address byte, with the R/W bit set to 1, the master must first perform a "dummy" write operation. The master issues a start condition and a slave address byte, receives an acknowledgement, and then issues the byte address. Immediately after acknowledging receipt of the byte address, the master issues another START condition and the slave

The address byte with the R/W bit set to 1. This is followed by an acknowledgment from the device, followed by the 8-bit control register. The host terminates the read operation by not responding to the acknowledgment and then issuing a stop condition. • The device is in a low-power standby state for address, acknowledgement, and data transfer sequences.
• The WEL bit is set to "0". In this state, the device cannot be written to.
• The SDA pin is in input mode.
The reset/reset signal is valid for t-explosion. Data protection has included the following circuits to prevent accidental writes:
• The WEL bit must be set to allow write operations.
• The correct clock count and bit sequence are required before the stop bit in order to start the nonvolatile write cycle.
• A three-step sequence is required before writing to the control register to change the watchdog timer or block lock settings.
• When held high, the wp pin prevents all writes to the control register.
• Below the vtrip voltage, communication with the device is disabled.
• If a reset/reset is active while it is in progress, the command to change the control register will be terminated.

notes:
1. These package sizes are within the allowable size range of jedec mo-187ba.
2. Dimensions and tolerances are in accordance with ANSI Y14.5M-1994.
3. Dimension "D" does not include mold flash, protrusions or gate burrs and is measured on the reference plane. Mold flash, protrusions and gate flash must not exceed 0.15mm (0.006 inches) per side.
4. Dimension "e1" excludes pilot arc flashes or protrusions and is measured on a reference plane. Pilot flashes and protrusions must not exceed 0.15 mm (0.006 in) per side.
5. The formed wire should be 0.10 mm (0.004) on the seat surface.
6. "L" is the length of the terminal to be soldered to the substrate.
7. "n" is the number of end positions.
8. Terminal numbers are for reference only.
9. Dimension “B” does not include dam protrusions. At maximum material conditions, the allowable total dam protrusion dimension shall exceed the "B" dimension by 0.08 mm (0.003 in). The minimum spacing between protrusions and adjacent wires is 0.07mm (0.0027 inches).
10. The datum shall be determined on the datum plane.
11. Control size: mm. Converted inch dimensions are for reference only.