Features

Flexible power supply from 5V to 12V

Power conversion input as low as 1.5V

1%output voltage accuracy

Large current integration Driver

The output voltage can be adjusted

0.8V internal benchmark

Simple voltage mode control loop

No sensor and programmable OCP

Low-side RDSON

The internal fixation of the oscillator is fixed at 300kHz

Internal soft start

ls-less management pre-pressure start

123] OV/UV Protection

FB disconnecting protection

SO-8 packaging

Application

subsystem power supply (MCH, Ioch, PCI ...))

Mascies and terminal power supply

CPU and DSP power supply

distributed power supply

General DC/DC converter

Instructions [123 ]

L6727 is a single-phase antihypertensive controller integrated large current driver, which provides complete control logic, protection and reference voltage to achieve simple and easy-to-universal DC-DC converter SO-8 packs. Equipment flexibility allows management to transform the power supply input VIN as low as 1.5V and the equipment power supply voltage between 5V and 12V. L6727 provides a simple control circuit voltage mode error amplifier. Integrated 0.8V benchmark allows the adjustment of the accuracy of the output voltage to change within the line and temperature range of ± 1%. The internal oscillator is fixed to 300kHz. L6727 provides programmable over -current protection and overvoltage and underwriting. The RDSON that monitor the current information span of MOSFET saves the resistance of the use of expensive and occupying space to monitor the output voltage through the FB pin. FB disconnect protection to prevent excessive and dangerous output voltage FB pins when floating.

Electricity

(VCC u003d 12V; TA u003d -20 ° C to+85 ° C, unless there are other regulations).

Electric characteristics (continued)

(vcc u003d 12V; TA u003d -20 ° C to+85 ° C, unless there are other regulations).

1. Design guarantee, without testing.

Device description

L6727 is a single -phase PWM controller, a built -in large current drive, providing complete control logic and protection, and realizing one in a simple and easy wayA general DC DC antihypertensive converter. The design is used to drive the N -channel MOSFET topology structure in the synchronous buck. Due to its high integration, the 8 -pin device allows reduction of cost and dimensional power solution. L6727 is designed to work through 5V or 12V power bus. Thanks to the high -precision 0.8V internal reference, the output voltage can be accurately adjusted to the line and temperature change range below 0.8V (between 0 ° C and+70 ° C), and the accuracy is ± 1%. The switch frequency is set to 300kHz inside. This device provides a simple control loop and a voltage mode error amplifier. The error amplifier has a 15MHz gain bandwidth and 8V/μs conversion rate, which allows high -fast transient response regulator bandwidth. Provide L27 overload protection to avoid overvoltage damage, under pressure and feedback disconnection protection. When the device is powered by 5V, the over -current check threshold can be programmed by a simple resistor. The output current is monitored by RDSON, which is surveillance across the low side MOSFET, saving sensors with expensive and occupying space. The output voltage and feedback are disconnected through the FB pin. L6727 realizes soft start, and the internal reference voltage is increased from 0V to 0.8V (typical values) within 5.1ms. The low -side non -function allows the device to perform soft start -up pre -voltage output to avoid negative peaks appearing through the high current return and risk load side of the output sensor.

Different types of integrated FET drives also allow multiple MOSFETs with high -power MOSFETs to reduce equivalent RDSON) to maintain fast switching conversion. The driver of the high -voltage side MOSFET uses a starting pin to power, and the phase pins are used to return. The driver of the low side MOSFET uses the VCC foot to power, and the GND tube foot is used for circuit. This controller contains a reflex wearing and adaptive dead zone control, which is low at the minimum side diode in the side diode. While maintaining good efficiency, it saves the use of the Schottky diode:

In order to check the high -voltage side MOSFET Pass Broken, detect phase pins. When the voltage decreases at the phase pin, the low side MOSFET gate driver is suddenly applied;

In order to check the low -voltage side MOSFET closed, the LGATE pin was detected. When the voltage at LGATE drops, the high -voltage side MOSFET gate driver is suddenly applied. If the current in the inductors is negative, the voltage on the phase will never decrease. By the allowable MOSFET to be allowed, even in this case, the door dog controller is enabled: if the source of the high side MOSFET does not decrease, the low -side MOSFET is the negative current of the allowable sensor to be connected. This mechanism allows the system to adjust even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any allowable conversion bus (see Table 5) The maximum working cycle restriction and recommended working conditions in Table 5 can be freely selected.

Power consumption

For high -sides MOS FETFET and high -sides: 27 are low -current drivers and then important to consider the energy consumed by the device in the process of driving them to avoid overcoming the maximum work temperature. There are two main factors affecting the power consumption of the device: bias power and driver power. Device bias power (PDC) depends on the provision of pins, which can be simply quantified (assuming that HS and LS have the same VCC device driver):

Driver driver The power supply is the driver's continuous opening and closing the external MOSFET; it is the MOSFET selected by the function of the switch and the function of the total grid charge. Considering that the total power PSW can quantitatively dissipate the switch MOSFET (easy to calculate) by three main dissipation factors: external grid resistors (if existence), MOSFET resistance, and inherent drive resistance. The last semester is an important period of computing equipment power consumption for our determination to do. Total power consumption of MOSFETS results:

Among them, VBoot-VPHASE is the voltage on the capacitor.

The external gate resistance helps the device to dissipate the switch power, because the power PSW will be shared between the internal driver impedance and the external resistor, resulting in a general cooling of the device.

Soft start and disable

L6727 realized soft startup to charge the output filter smoothly to avoid the current required for high -bearing input power supply. The device gradually increases the internal reference voltage from 0V to 0.8V, about 5.1ms. It is closed -loop adjustment and gradually charging the output capacitor to the final adjustment voltage. If the current is triggered during the soft startup, the overcover softening sequence will be launched, and the remaining time of the internal soft start will be closed (up to 2048 clock cycles) plus the 2048 clock cycle, and a new soft start. Only when the VCC power supply is higher than that of the UVLO threshold, the device begins to start the soft start -up phase of the current threshold setting stage.

There is no startup (LSLESS)

In order to manage the startup output of the pre -partial output, L6727 is activated by LS drive: In the soft start -up stage, the LS drive results are disabled (LS u003d OFF) until until) until the OFF) until it is prohibited (LS u003d OFF) until it is prohibited (LS u003d OFF) until it is prohibited (LS u003d OFF) until until) HS starts switching. This avoids the voltage that may occur when the risk negative peak on the output starts on the pre -deflection output. If the output voltage is biased to the voltage below the programming voltage in advance, unless the slope starts the slope to exceed the output pre -biased voltage, LS will turn on; then VOUT will rise from there without any reduction or current return. If the output voltage is biased in advance to a voltage higher than the programming voltage, HS will not start switching. In this case, at the end of the soft start time, LS is enabled and discharged to the final adjustment value. This special feature of this device only shields LS from the control loop point to open the point of view: protect the bypass without LSFET, and open the LS MOSFET when needed.

Enable/disable

below 0.5V (typical values), the device can be disabled by pushing COMP/DIS pins outside. The disabled HS and LS MOSFET are closed, and the 20μA current comes from compensation/display pins. Release the pin, the current will pull it over the threshold, so that the device allows the device to execute the new SS again. To disable the device, the COMP output current of 10mA needs to be overdone is about 15 μs. Once disabled, the COMP output current will be reduced to 20μA.

Over current protection

Overcurrent features are protected from short -circuit output or overload sensing through the following ways. Output current information, RDSON. This method can avoid the use of expensive and occupying a sensing resistance. The low -voltage side RDSON current detection is held internally when the LS MOSFET is opened with a programming OCP threshold voltage. If the monitored voltage drop (GND to phase) exceeds this threshold, the current event is detected. If two consecutive detection of two over -current events switching cycles, the protection will be triggered, and the device will turn off the MOSFET of the LS and HS2048 clock cycle (plus the internal SS remaining time, if it is triggered during the SS period, and it will start a new one. Soft start. If the current situation is not eliminated, the continuous failure will cause the L6727 to enter a typical cycle of 13.6ms interrupt mode (Figure 5) to ensure safety load protection and very low power consumption.

overcurrent threshold value Set

When VCC u003d 5V is provided, L6727 allows easy programming to program over the current threshold range from 50mV to 500MV, just in the COMP and VCC. ) (Given VCC end the UVLO threshold), the internal 60 μA current (IOCSET) sinks from the COMP pin to determine the voltage drop through the ROCSET. The current threshold before the cycle. Differential sensor and VCC allow the OCSET program to be completely independent of the vehicle identification number track. The total time range of the OC settings program from 5.5ms to 6.5ms, proportional to the setting threshold. Connect between COMP and VCC ROCSET resistance, the threshold of programming settings sets Belgium:

The range of the RocSet value is 2.5K u0026#8486; to 25K u0026#8486;. The system will be very sensitive to the initiative and noise. This may lead to continuous OCP trigger and hiccup mode. In this case, consider increasing ROCSET value. If the ROCSET is not connected (and VCC u003d 5V), the device will set the maximum value threshold. If the VCC of the device is higher than 7V, the ROCSET shall not be connected. In this case, once VCC rises to VCC_OC (8V typical value), L6727 switches the OC threshold to 400 MV (internal fixation). OC threshold settings and soft startup oscilloscope sampling waveforms are shown in Figure 5

Output voltage monitor and protection

L6727 monitor the voltage at the FB pin, and compare it in order to compare it with the internal reference voltage Provide under pressure and overvoltage protection.

Impurd voltage protection

If the voltage at the FB pin drops below the UV threshold (0.6V typical value), the device will turn off two HS and LS-MOSFETS will wait for 2048 clocks The cycle, then execute the new soft start. If the voltage conditions are not eliminated, the device enters the interrupt mode, and the typical cycle is 13.6 milliseconds. At the end of the soft start, UVP is in a state of activity.

Overvoltage protection

If the voltage at the FB pins increases more than the OV threshold (1V typical value), the overvoltage protection is closed as the overvoltage is detected. Once the current threshold setting stage appears, OVP has always been completed at the highest priority activation.

Feedback disconnection protection

In order to provide load protection without connecting the FB pin, the 100NA bias current is always from this pin. If the FB pin is not connected, the current will permanently rise FB exceeding the OVP threshold: Therefore, LS will be locked to prevent the output voltage increase control.

Obscashed lock

In order to avoid the abnormal behavior of the device when the power supply voltage is too low to support its internal orbit, UVLO: When the VCC is reached, the device will start the upper limit of the UVLO. When VCC is lower than UVLO than UVLO The lower limit threshold will be closed. 4.1V's maximum UVLO upper limit allows L6727 to from the bus from 5V and 12V power supply diode configuration.

Application details

Output voltage selection

L6727 can accurately adjust the output voltage below of as low as 0.8V with a fixed 0.8V internal benchmark to ensure the output adjustment voltage voltage In the range of ± 1%, the temperature changes between 0 ° C and+70 ° C, excluding the output resistance). The output voltage is higher than 0.8V. It can easily increase the FB pins and grounding between the resistance ROS. For Figure 1, the DC output voltage is:

Among them, VREF is 0.8V.

Compensation network

The control loop shown in FIG. 6 is the voltage mode control loop. The error placing is a voltage mode type. The output voltage adjustment is internal benchmark(If you exist, in the control loop calculation, you can ignore the offset resistance between FB nodes and GND). Error amplifier output is compared with the oscillator sawtooth wave to provide PWM signals to the cab. Then PWM signal is transmitted to the access node amplitude through VIN. The waveform is filtered by the output filter. The transmission function of the converter is the small signal transmission function EA and VOUT between the output. This function has a bipolar at the frequency FLC, depending on the resonance of L-Cout at the FESR and zero point depends on the output capacitance ESR. The DC gain modulation is the input voltage VIN except the peak to the peak oscillator voltage u0026#8710; Vosc. The compensation network is ideal to-ZF/ZFB through transmission to close the connection VOUT and EA output.

The target of compensation is to close the control circuit to ensure that the DC regulation accuracy is high, good performance and stability. To achieve a high -gain ring, high bandwidth and good phase margin. To achieve high DC gains, the compensation network transmission has the shape of the integral device. The ring bandwidth (F0DB) can be fixed by selecting the appropriate RF/RFB ratio, but the stability should not exceed FSW/2π. In order to obtain a good phase margin, the control circuit gain must be passed through the 0DB axis at the -20DB/Decade slope. As an example, Figure 7 shows the closer Bode diagram of type III compensation.

In order to determine the pole and zero point of the compensation network, the following suggestions can follow:

A) Set the gain RF/RFB to obtain the required closed -loop regulator Bandwidth is based on the approximate formula (RFB's proposed value range is 2K u0026#8486; to 5K u0026#8486;):

E) Check whether the compensation network gain is lower than the opening of the opening EA EA gain ;

f) It is estimated to be obtained (should be greater than 45 °) and repeat it. If necessary, modify the parameters.

Layout Guide

L6727 provides control functions and large current integrated drives to achieve a large current antihypertensive DC-DC converter. In this application, a good layout is very important and important. The first priority when placing components for these applications must be retained to the power supply part to minimize the length of each connection and circuit. To connect the noise and voltage peak (EMI and loss) power supply (highlighting the display graph 8) must be part of the power supply plane, and it must be tracked with wide and thick copper anyway: the cycle must be minimized. Key components, that is, power MOSFET, must approach each other. It is recommended to use a multi -layer printing circuit board. Input a capacitor (CIN), or a part of the total capacitance at least, must be placed near the power segment to eliminate traces of copper. Low ESR and ESL capacitors are the first choice,MLCC is recommended to connect near the HS drainage pipe. When the power trace line must be to reduce the parasitic resistance and inductance of PCB. Furthermore, copying the same high -current trajectory on multiple PCB layers will reduce parasitic resistance related to that connection. Connect the output large -capacity capacitor (COUT) to the position closer to the load as much as possible, minimize the inductance and resistance related to the parasitic and copper traces, and increase the additional off -coupled electric container to the load. Bulk capacitors banks.

The size of the door trajectory and the phase trajectory must determine the power MOSFET according to the divers being transmitted. The robustness of the device allows management applications with powerful functions to stay away from the controller without losing performance. In any case, if possible, it is recommended to minimize the distance between the controller and the power part. See Figure 9 for the current path of the driver. The connection between small signal components and application key nodes, as well as power supply to the device, is also important. Positioning the barrier container (VCC and self -lifting capacitors) and circuit compensation elements as close to the device as practical as possible. In order to realize the programmability of overcurrent, the ROCSET is close to the device and avoids the leakage current path on the COMP/OC pin because the internal current source is only 60 μA. The system that does not use the Schartki diode and the low -edge MOSFET may show a large number of negative peaks on a large number of defect phase needles. The peak must be limited to the rated value within the absolute maximum range (for example, a gate resistance is connected in series on the HS MOSFET gate, or a phase resistance string is connected to the pilot), but there is an additional result: resulting Self -up capacitors are overcharged. This additional cost can be reasons. In the stomach of the worst input voltage, the phase voltage is started to overcome the absolute maximum rated value and cause the device to fail. In this case, it is recommended to add a small resistance to the self -raising diode (RD in Figure 1)

embedded in the L6727 -based VRS

] When embedding virtual reality into the application, you must be extra careful, because VR is a switch -type DC/DC regulator. The most common system that must work in it is the digital system, such as MB or similar system. In fact, the latest MBS becomes faster and faster: high -speed data bus is becoming more and more universal and switching noise. If it does not follow other layout guidelines, the data generated by VR may affect data integrity. When selecting a large path with a large amount of switching, a few simple point current flows must be considered (the high current of the switching and the high current will cause the trace line of the voltage spikes on the mixed inductor to affect the nearby trace line): When on the inner layer, When copying the high current path, keep the size of all layers the same to avoid the ""surrounding"" effect to increase noise coupling. Maintain a safe protection distance between the large current switch VR trajectory and the data bus, especially high -speed data bus to reduce noise coupling. For I/O sub -systemWhen the uniform deviation is tracked, keeping a safe protection distance or appropriate filtering must be walked near VR.The possible cause of noise may be located in phase connection, MOSFETS gate driver, and input voltage path (from input large -capacity capacitors and HS drain).If you do not insist on using the power ground plane, you must consider it.These connections must be careful of the data bus that is sensitive to noise.Because the noise generated is mainly due to the switching activity of VR, the noise transmission depends on the speed of the current conversion.In order to reduce the level of noise emissions, it is also possible. In addition to the previous guidelines, in order to reduce the current slope and increase the switching time: because the switching time is longer, this will cause the switch loss that must be considered in the system thermal design.