The DAC7800 , DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS multiplying digital-to-analog converters (DACs). Digital interface speed and AC multiplication performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true 12-bit integral and differential linearity over a wide industrial temperature range of -40°C to +85°C.

The DAC7800 has a serial interface capable of inputting data at a rate of at least 10MHz. Serial data is first clocked (edge-triggered) MSB into a 24-bit shift register and then latched into each DAC individually or simultaneously, as required by the application. Asynchronous CLEAR control is provided for power-on reset or system calibration functions. It comes in a 16-pin 0.3-wide plastic DIP package.

The DAC7801 has a 2-byte (8+4) double-buffered interface. For each DAC, the data is first loaded (level shifted) into the input register in two steps. Then both DACs are updated simultaneously. The DAC7801 has an asynchronous CLEAR control function. The DAC7801 is available in a 24-pin 0.3 wide plastic DIP package. The DAC7802 has a single buffered 12-bit data word interface. Parallel data is loaded (edge-triggered) into a single DAC register per DAC. The DAC7801 is packaged in a 24-pin 0.3 all plastic DIP package.

circuit description

figure 1

Figure 1 shows a simplified schematic of a half DAC780x. 12 SPDT CMOS switches that switch current from V to REF A pin I toggle between OUT A and AGND. This maintains a constant current in each leg of the ladder considering the following less input code. The input resistance at V is therefore constant and can be driven by either voltage or current, AC or DC, positive or negative polarity, and has a voltage range of up to ±20V. A CMOS switching transistor comprises a series ladder termination resistor and a feedback resistor RFB one connected in series to compensate for a temperature drift resistance ladder switch connected in series. Figure 2 shows the equivalent circuit of DAC A. ?OUT is due to the N-channel switch and the output capacitance varies from approximately 30pF to 70pF with the digital input code. The trend/surge source ILKG is the combined leakage age of the surface junctions onto the substrate. My LKG roughly doubles every 10°C. RO is the equivalent output impedance of the DAC and its variation with the input code.

ESD protection

All digital DAC780X inputs include on-chip ESD protection circuitry. This protection is designed to withstand 2.5kV (using the Human Body Model, 100pF and 1500Ω). However, industry standard ESD protection methods should be used when handling or storing these components. When not in use, devices should be stored in conductive foam or rails. The foam or rail should drain to the destination device before the socket potential is removed.

figure 2

power connection

The DAC780X is designed to operate at V DD=+5V+10%. For best performance and noise rejection, a power supply decoupling capacitor ?D should be added as shown in the application circuit. These capacitors (1µF tantalum recom- unexpected) should be close to the DAC. AGND and DGND should be connected together at only one point, preferably at the power ground point. Individual re-turns reduce the current flow of the low-level signal if the correct path is connected. The output op-amp, analog common (+input) should be connected as close to the AGND pin of the DAC780X as possible.

Wiring Precautions

To design a printed circuit board to minimize AC feedthrough, care should be taken to reduce capacitive coupling between the BE-tween the VREF line and the IOUT line. Also, coupling between capacitive DACs can compromise the channel-to-channel isolation. Coupling from any digital control or data lines may degrade glitch and digital crosstalk performance. Soldering the DAC780x directly to the PC board does not have a socket. Sockets add parasitic capacitance (which degrades AC performance).

Amplifier offset voltage

The output amplifier used by the DAC780x should have a low input offset voltage to maintain the linearity of the transfer function. The amplifier's voltage output has an error component that is multiplied by the op-amp's bias voltage in a "noise gain" circuit. This "noise gain" is equal to (RF/RO+1), where RO is the output impedance of the DAC IOUT terminal and RF is the impedance of the feedback network. The nonlinearity occurs due to the variable code with the output impedance. If the 0-yard case is excluded (where RO = infinity), the RO will vary from R-3R to provide a "noise gain" variation of 4/3 and 2. In addition, the variation of R between O is nonlinear with code, and the largest step O in R occurs in large code where the worst differential nonlinearity of transition is also likely to be encountered. It can be seen that the nonlinear output of the amplifier is 2VOS–4VOS/3=2VOS/3. Therefore, in order to maintain a good nonlinear op amp the offset should be much less than 1/2LSB.

image 3

Unipolar CON group fi guration

Figure 3 shows the DAC780x in a typical unipolar (two-quadrant) multiplying configuration. Analog output values and digital input codes are listed in the table. The amplifier used in this circuit can be a single amplifier such as the OPA602 or a dual channel amplifier such as the OPA2107. C1 and C2 provide phase compensation to reduce settling time and overshoot when using high speed op amps. If the application requires a DAC with zero gain error, the circuit shown in Figure 4 can be used. Resistors R2 and R4 induce a positive gain error greater than the worst case initial negative gain error. Trimming resistors R1 and R3 provide variable negative gain error with sufficient adjustment range to correct for the worst-case initial positive gain error plus the error produced by R2 and R4.

Figure 4

surface