The HI5746 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. The circuit shown in Figure Analog Input Sample and Hold is used for front-end differential differential output sample analysis and hold (S/H). The switch is controlled by an internal sampling clock, which is a non-overlapping two-phase signal, φ1 and φ2 from the main sampling clock. In the sampling phase, φ1, the input signal is applied to the sampling capacitor, CS. At the same time the holding capacitor, CH, is drained to analog ground. The input signal is sampled on the falling edge φ1 of the sampled baseplate capacitor. At the next clock phase, φ2, the two backplane sampling capacitors are connected together, and the hold capacitor switches to the output node of the op amp. Charging then redistributes C between S and CH after one sample-and-hold cycle. The front-end sample and hold output is a fully differential, representative analog input for sampled data. This circuit not only performs the sample and hold function, but also converts a single-ended input to a fully-differential output converter core. During the sampling phase, the VIN pin only sees the on-resistance of the switch and CS. The relatively small values of these components result in a typical full power input bandwidth of a converter of 250MHz.

Functional block diagram

Analog input sample and hold

As shown in the functional block diagram and timing diagrams in the accompanying drawings, eight identical pipeline subconverter stages, each containing a 2-bit FL ash converter and a 2-bit multiplying digital-to-analog converter, follow the S/H circuit with The ninth level is a 2-bit Florida Gray converter. Each conversion stage in the pipeline will be sampled in one phase and amplified in the other clock phase. Each subconverter clock signal is offset 180 degrees from the resulting alternating previous stage's clock signal stage in the pipeline to perform the same operation. Each of the eight identical 2-bit subconverter output stages is a two-bit digital word containing complementary bits to be used by the digital error correction logic. The output of each subconverter stage is input to the digital delay line controlled by the internal sampling clock. The function of the digital delay line is to time-align the 8 digital outputs to the same 2-bit subconverter stage with the corresponding ninth stage flasher before applying the output 18-bit result digital error correction logic. The digital error correction logic uses the complementary bits to correctly generate the final top ten bits of the converter's digital data output for any errors that may exist. Due to the nature of the pipeline of this converter, the analog input samples of the digital data representation are output to the samples of the digital data bus on the 7th cycle after the analog of the clock. This delay for a specific network connection is coded as the data latency. After the data delay time, the digital data represents each successful analog sample output in the subsequent clock cycle. Digital output data is buffered via a dual-sync to an external sample clock latching technique. The digital error output correction circuit has two's complement or offset binary format selection (DFS) control inputs according to the state of the different data formats.

Timing diagram

Reference voltage input

VREF- and VREF+ The HI5746 is designed to accept two external references at the VREF input pin. Typical operation of this converter requires the VREF+ key to be set at +2.5V and VREF- to be set to 2.0V. However, it should be noted that the input at the V structure REF+ and VREF- input pins are connected by a resistor divider in which a resistor (nominal 500Ω) is connected between V REF+ and VREF- and the divider ( Nominally 2000Ω) other resistors connected between REF- and analog ground. This allows the user to supply only the +2.5VV option with the REF+ reference and the +2.0V VREF- voltage divider generated internally by the input structure. The HI5746 is tested with VREF- equal to +2.0V and VREF+ equal to +2.5V to produce a fully differential analog input voltage range of ±0.5V. VREF+ and VREF- can be different voltages from above. To minimize total converter noise, it is recommended to provide two reference voltage input pins, VREF+ and VREF-, with sufficient high frequency decoupling.

AC coupled differential input

analog input

Connecting the analog input differentially to the HI5746 is a differential input that can be configured in various ways depending on the signal source and the desired performance level. A fully differential connection (Figure AC coupled differential input and Figure DC coupled differential input) will give the best performance for the converter. Since the HI5746 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For differential input connections this means that the analog input common mode voltage ranges from 0.25V to 4.75V. The performance of the ADC does not vary significantly with the value of the analog input common-mode voltage. A DC voltage source, VDC, equal to 3.2V (typ), is provided by the user to help simplify circuit design when using AC-coupled differential inputs. This low output impedance voltage source is not designed to be a reference, but makes an excellent DC bias source and maintains good analog temperature over the input common-mode voltage range. For AC-coupled differential inputs (Figure AC-coupled differential inputs) assume the difference between VREF+ is typically 2.5V, while VREF-, typically 2.0V, is 0.5V. Full scale is achieved when VIN and -VIN input signals are 0.5VP-P combined with -VIN present 180 degrees to VIN. The converter will be at positive full scale when the VIN+ input is at VDC+ 0.25V and the VIN- input is at VDC- 0.25V (VIN+ -VIN- = +0.5V). Instead, the converter will be at negative full scale when the VIN+ input is equal to VDC-0.25V and VIN- is at VDC+0.25V (VIN+ - VIN- = -0.5V). The analog input can be DC coupled (Figure DC-coupled differential input ), as long as the input is within the analog input common mode voltage range (0.25V≤VDC≤4.75V). Resistor R, which is completely unnecessary in Figure 27 but can be used as a load setting resistor. A capacitor, C, from V IN+ to VIN- helps filter any high noise at the input frequency and also improves performance. Values around 20pF are soooo old and can be used in AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the frequency components of the highest analog input signal.

DC coupled differential input

Analog input

The single-ended connection shown in the figure AC-coupled single-ended input can be used with single-ended AC-coupled inputs. Again, assume the difference between VREF+, which is typically 2.5V, and VREF-, which is typically 2V, is 0.5V. If VIN is a 1VP-P sine wave, then VIN+ is 1VP-P at the positive sine wave riding voltage equal to the DC voltage. The converter will be at positive full scale when VIN+ is VDC+0.5V (VIN+ - VIN- = +0.5V) and will be at negative full scale when VIN+ is equal to VDC-0.5V (VIN+ - VIN- = -0.5V) . SUF cient some headroom is provided so that the input voltage never goes above +5V or below AGND. In this case, the DC voltage can be between 0.5V and 4.5V without a significant change in ADC performance. The easiest way to generate a DC voltage is to use a DC bias source, VDC, at the output of the HI5746. Single-ended analog inputs can be DC-coupled (Figure DC-coupled differential inputs), as long as the input is within the common-mode voltage range of the analog input. Resistor R, is not absolutely necessary in the DC-coupled single-ended input shown in the figure, but can be used as a load-setting resistor. A capacitor, C, from V IN+ to VIN- helps filter any high noise at the input frequency and also improves performance. Values around 20pF are soooo old and can be used in AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the frequency components of the highest analog input signal. Single-ended sources can provide better overall system performance if the network is first converted before driving the HI5746 poorly.

AC-coupled single-ended input

Digital Output Control and Clock Requirements

The HI5746 provides a standard high-speed interface to the external TTL logic family. To ensure the HI5746, the duty cycle of the rated performance clock should be within 50% of the period of ±5%. It must also have low jitter and standard TTL level operation. The performance of HI5746 will only be guaranteed if the conversion rate is greater than 1 MSPS. This ensures proper internal dynamic circuit performance. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sampling rate higher than 1 MSPS will have to be executed before valid data is available. The Data Format Select (DFS) pin setting determines the format of the digital data output. When at logic low, data will be output in offset binary format. At level 2, when logic high, the data will be output in two's complement format.