Using Evaluation Committee: XOCLC6EVB Equipment: NBXXXXX Prepared by: Senad Lomigora, Casey Stys and Paul Shockman
Description This evaluation board manual (xoclc6evb/d) is a guide for using the xoclc6evb evaluation board for quick evaluation, characterization, and verification of the NBBXXX family of clock oscillator modules (packaged in a 6-pin CLCC, 5mm by 7mm, Case 848ab) device provides a convenient platform for performance and operation (see appendix).
Devices in this family provide an internal crystal and PLL integrated circuit. This Evaluation Board Manual and Evaluation Board should be used in conjunction with specific equipment data sheets containing complete technical details regarding specifications and operation.
The NBXXXXX Clock Oscillator Module devices can be solder mounted directly on the available evaluation board packages; or a separate plug-in socket (P/N AM0393−320R from SER Electronics) can be solder mounted onto the available packages to insert and test multiple unit.
Evaluation Board Features • 6-pin CLCC solder joints for mounting equipment or solder joints for test sockets • Integrated jumper headers for easy manual control of the levels of the "Output Enable" (Pin 1) and "Frequency Select" (Pin 2) pins .
• Enable single-supply or split-supply operation.
The LVPECL differential outputs are accessed through SMA connectors that provide different output load configurations.
Evaluation Board Manual Documentation Features • XOCLC6EVB Evaluation Board Information • Appropriate Lab Setup and Procedures • Board Fabrication Bill of Materials • Evaluation Board Schematic
- Mechanical enclosure outline - general marking diagram
-What kind of measurements do you want for the solder traces?
With this evaluation board, the following measurements can be made in single-ended or differential mode of operation. • DC Characteristics • Frequency Performance • Output Rise and Fall Time • Phase Noise • Jitter

The installer should follow the steps below to properly set up the device.
Step 1: Turn on the power (split power mode)
Three power levels must be provided to the board: V, unload, and SMAGND through the test point anvil on the edge of the board. Bypass capacitors are installed near the test points, from V to SMAGND and from DUGND to SMAGND (see BOM). The unit can be tested in one of three power modes (see Table 3): DDDD
A) Single (positive) +3.3 V setup with no offset to supply or output levels
B) The split 3.3 V setup shifts V, dutgnd, and output voltage levels by −1.3 V, avoiding an additional separate V supply and allowing direct connection to test equipment such as an oscilloscope or counter, with a 50 Ω impedance to the GND input. smagnd=vtt=vdd–2.0V=0.0V. DDTT
C). The single (negative) −3.3 V setting offsets V, Dutgnd, and the output voltage level by: DD
3.3V

Note: SMAGND is the SMA cable shield reference for input and output only, not to be confused with the device ground pin (which is grounded).
Step 2: Connect Output Signals Table 4 lists specific logic levels with their appropriate power supplies and typical laboratory setup conditions.
LVPECL: The lvpecl output has a standard, open emitter output that must be externally DC loaded and AC terminated. The split power supply technique utilizes 50 of the LVPECL outputs terminated to an oscilloscope or frequency counter. Since vtt = vdd – 2 V, shifting vdd to +2.0 V produces vtt = 0 V or ground (smagnd). The V terminal is connected to the isolated SMAGND connector ground plane, not to be confused with the device ground pin (dutgnd). (See Application Note AN8020/D for details on ECL termination). TT
Chronic Myeloid Leukemia: For CML lab setup and testing, operation with a negative supply voltage is recommended so that the 50 Ω internal impedance in the oscilloscope serves as a termination for the CML signal (V=0.0 V, Smagnd=0.0 V, Dutgnd=−3.3 V ) (see application note AN8173/D for details on CML termination). DD
lvds step 3: configure fsel and oe: The driver terminations are 100 resistors on the differential lines at the receiver input. The fsel and oe control pins can be controlled from an external source via appropriate test points, or via

Split power lab setup for LVPECL output (do not cross ground wire ground and SMAGND)

Note: For CML output, 50 to VDD is required for proper termination. See application note and 8173/D.

Typical lab setup for CML output (without jumper ground and SMAGND)

XOCLC6EVB Evaluation Board Schematic

Evaluation Board Fabrication Instructions
1. Material: FR-4
2. The finished copper is Loz. (0.0014) outer layer
3. Minimum copper thickness is 0.0007" for plated through hole annular rings, minimum thickness is 0.0002"
4. LPI welding mask green
5. Welding mask registration 0.002" not applicable
6. All exposed copper areas are gold plated (0.000030" gold over 0.000100" nickel)
7. If specified, the screen shall be white epoxy ink.
8. The hole diameter tolerance is 0.002", the maximum interlayer mismatch shall be 0.004", and the measurement method must be in accordance with MIL-P-55110D, Figure 1.
9. The deviation of the width of the finished wire from the Artwork Master shall not exceed 0.001", and the width of 50 traces shall be 0.024".
10. Bend and twist shall not exceed 0.002" per inch for single panels and 0.010" per inch for multi-layer panels.
11. All dimensions are in inches unless otherwise specified. XX 0.010 "XXX"
0.004".
12. According to the acceptability requirements of IPC-A-600E.
13. View the drawing from the component or main face.
14. This is a 4-layer board.
15. All holes are plated through holes unless otherwise specified.
16. Drill dimensions are in thousandths of an inch.
17. Trim any silkscreen through holes or patches.
18. All sharp edges should be broken off and the edges of the printed circuit board should be smooth and even