General Description The W25Q64 FV (64M-bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. The flexibility and performance of the 25Q series far exceeds that of ordinary serial flash memory devices. They are ideal for code-behind into RAM, execute code directly from dual/quad SPI (XIP), and store voice, text, and data. The device operates on a single 2.7V to 3.6V supply with current consumption as low as 4mA and 1µA when powered down. All devices come in space-saving packaging. The W25Q64FV array is organized into 32768 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), 128 groups (32KB block erase), 256 groups (64KB block erase), or the entire chip (chip erase). The W25Q64FV has 2048 erasable sectors and 128 erasable blocks. Small 4KB sectors allow greater flexibility in applications requiring data and parameter storage The W25Q64FV supports standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI, and 2CLOCK instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). Supports SPI clock frequencies up to 104MHz, allowing dual I/O equivalent clock rates of 208MHz (104MHz x 2) and quad I/O equivalent when using fast-read dual/quad I/O and QPI instructions The clock rate is 416MHz (104MHz x 4). These transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash. The sequential read mode allows efficient memory access, and the instruction overhead of reading a 24-bit address is only 8 clocks, allowing true XIP (execute-in-place) operations. A hold pin, write protect pin and programmable write protect, with top or bottom array control, provide further control flexibility. Additionally, the device supports jedec standard manufacturer and device identification, a 64-bit unique serial number, and three 256-byte security registers. 2. Features SPIRash Memory Family – W25Q64FV: 64Mbits/8Mbytes (8388608) – Standard SPI: CLK, /CS, DI, DO, /WP, /HOLD – Dual SPI: CLK, /CS, IO0, IO1, /WP , /HOLD – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – QPI: CLK, /CS, IO0, IO1, IO2, IO3 Highest Performance Serial Flash – 104MHz Standard / Dual/Quad SPI Clock – 208/416MHz Equivalent Dual/Quad SPI – 50MB/s Continuous Data Transfer Rate – Over 100,000 Erase/Program Cycles – Over 20 Years of Data Retention High Efficiency “Continuous Read” and QPI Modes – 8/16/32/ 64 bytes of sequential reads – AS address memory only 8 clocks – Quad Peripheral Interface (QPI) reduces instruction overhead – Allows true XIP (execute in place) operations – Better than x16 parallel flash Low power, wide temperature Range – Single 2.7 to 3.6V Supply – 4mA Active Current, <1µA Power Down (typ.). ) – -40°C to +85°C Operating Range  Flexible Architecture with 4KB Sectors – Unified Sector Erase (4K Bytes) – Unified Block Erase (32K and 64K Bytes) – Each Programmable Page Program 1 to 256 Bytes – Erase/Program Suspend and Resume Advanced Security Features – Software and Hardware Rewrite Protection – Top/Bottom, 4KB Supplemental Array Protection – Power Lock and OTP Protection – 64-bit per device Unique ID – Found Parameter (SFDP) Register – 3x256 Byte Security Register and OTP Lock – Volatile and Nonvolatile Status Register Bits SPACE Efficient Packaging – 8-pin SOIC/VSOP 208 mil – 8-pin WSON 6x5 mm/ 8x6 mm – 8-pin XSON 4x4 mm – 16-pin SOIC 300 mil – 8-pin PDIP 300 mil – 24-ball TFBGA 8x6 mm – 16-ball WLCSP – Contact Winbond for KGD and other options

Pin Description The chip select (/cs) SPI chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (DO or io0, io1, io2, io3) pins are at high impedance. When deselected, the power consumption of the device is in standby unless an internal erase, program, or write status register cycle is in progress. When /cs goes low, the device will be selected, power consumption will increase to the active level, and instructions can write to the device and read data from the device. After power up, /cs must transition from high to low to accept new commands. The /cs input must track the VCC supply level at power up and power down. This can be done with pull-up resistors/cs if desired.
Serial data input, output and IOS (DI, DO and IO0, IO1, IO2, IO3) The W25Q64FV supports standard SPI, dual SPI, quad SPI and QPI operation. Standard SPI commands use the unidirectional DI (input) pins to serially write commands, addresses, or data to the device on the rising edge of the serial clock (CLK) input pin. Standard SPI also uses a unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual/Quad SPI and QPI instructions use bidirectional IO pins to serially write commands, addresses, or data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. Quad SPI and QPI instructions require the nonvolatile Quad Enable bit (QE) in Status Register-2 to be set. When qe=1, the /wp pin becomes io2, and the /hold pin becomes io3.
Write Protect (/wp) The Write Protect (/wp) pin can be used to prevent the Status Register from being written to. Used in conjunction with the block protection (cmp, sec, tb, bp2, bp1, and bp0) bits of the status register and the status register protection (srp) bits, a sector as small as 4kb or parts of the entire memory array can be hardware protected. The /wp pin is active low. However, when the qe bit of status register 2 is set to quad input/output, the /wp pin function is not available because this pin is used for io 2
Hold (/hold) The /hold pin allows the device to pause when the device is active. When /hold goes low, when /cs goes low, the do pin will be at high impedance and the signals on the DI and CLK pins will be ignored (don't care). When /holds high, device operation can resume. The /hold function is useful when multiple devices share the same SPI signal. The /HOLD pin is active low. When the QE bit of the status register-2 is set to quad input/output, the /hold pin function is not available because this pin is used for io3.
Serial Clock (CLK) The SPI serial clock input (CLK) pin provides timing for serial input and output operations.

Standard SPI commands access the W25Q64FV through an SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS), Serial Data In (DI), and Serial Data Out (DO). Standard SPI commands use the DI input pins to serially write commands, addresses, or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. The main difference between Mode 0 and Mode 3 is the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the serial flash. For Mode 0, the CLK signal is typically low on the falling and rising edges of /cs. For Mode 3, the CLK signal is normally high on the falling and rising edges of /cs.
Dual SPI Instructions The W25Q64FV supports dual SPI operations when using instructions such as "Fast Read Dual Output (3BH)" and "Fast Read Dual I/O (BBH)". These instructions allow data to be transferred to and from the device at 2 to 3 times the speed of a normal serial flash device. Dual SPI read instructions are ideal for quickly downloading code to RAM at power up (code shadowing), or executing non-speed critical code directly from the SPI bus (XIP). When using dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
power

The quad SPI command W25Q64FV is using "Fast Read Quad Output (6Bh)", "Fast Read Quad I/O (EBH)", "Word Read Quad I/O (E7H)" and "Oct Word Quad SPI operation is supported when reading instructions such as Quad I/O (E3H)”. These instructions allow data to be transferred to and from the device at four to six times the rate of normal serial flash. Quad-read instructions significantly increase sequential and random access transfer rates, allowing fast code-hiding or execution directly to RAM from the SPI bus (XIP). When using four SPI commands, the DI and DO pins become bidirectional IO0 and IO1, respectively, and the /wp and /hold pins become IO2 and IO3, respectively. The Quad SPI instruction requires the nonvolatile Quad Enable bit (QE) in Status Register 2 to be set.
qpi commands The w25q64fv supports Quad Peripheral Interface (QPI) operation only when the device is switched from standard/dual/quad SPI mode to qpi mode using the "enable qpi(38h)" command. A typical SPI protocol requires byte-long instruction codes to be transferred to the device only through the DI pins in the 8 serial clocks. QPI mode utilizes all four IO pins to input instruction code, so only two serial clocks are required. This can significantly reduce SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusives. Only one mode can be active at any given time. The "enable qpi(38h)" and "disable qpi(ffh)" commands are used to switch between these two modes. After power up or a software reset using the "Reset(99h)" command, the default state of the device is standard/dual/quad SPI mode. To enable QPI mode, the nonvolatile Quaternary Enable bit (QE) in Status Register-2 needs to be set. When using the qpi instruction, the di and do pins become bidirectional io0 and io1, respectively, and the /wp and /hold pins become io2 and io3, respectively.
Hold Function For standard SPI and dual SPI operation, the /hold signal allows W25Q64FV operation to be suspended when actively selected (when /cs is low). The /hold function can be useful if the SPI data and clock signals are shared with other devices. For example, when priority interrupts need to use the SPI bus, consider whether the page buffer is only partially written. In this case, the /hold function can save the state of the instruction and data in a buffer so that programming can resume where it left off once the bus is available again. The /hold function is only available for Standard SPI and Dual SPI operation, not Quad SPI or QPI.
To initiate the A/HOLD condition, the device must be selected with /CS low. If the CLK signal is already low, the A/HOLD (hold) state will activate on the falling edge of the /HOLD (hold) signal. If CLK has not been lowered, the /hold state will activate after the next falling edge of CLK. If the CLK signal is already low, the /hold condition will terminate on the rising edge of the /hold signal. If CLK has not fallen yet, the /hold state will be terminated after the next falling edge of CLK. In the A/HOLD state, the serial data output (DO) is high impedance and the serial data input (DI) and serial clock (CLK) are ignored. The chip select (/cs) signal should remain active (low) throughout the /hold operation to avoid resetting the device's internal logic state.

Write-protected applications using non-volatile memory must consider the possibility of noise and other adverse system conditions that could compromise data integrity. To solve this problem, the W25Q64FV provides several methods to protect data from accidental writes.
Write protection feature  Device reset when VCC is below threshold  Delayed write disable after power up  Write enable/disable instruction and automatic write disable after erase or program  Software and hardware (/wp pin) usage status Register write protection  Write protection operation using power down instruction  Lock write protection of status register until next power up  One time program (OTP) write protection of array and security registers using status register*
*Note: This feature is available on special orders. Please contact Winbond for details.
On power-up or power-down, the W25Q64FV will remain in the reset state while VCC is below the threshold of VWI (see power-up timing and voltage levels and Figure 43). On reset, all operations are disabled and instructions are not recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled within the time delay of the TPUW. This includes Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instructions. Note that the chip select pin (/cs) must track the VCC supply level at power-up until the VCC minimum level and TVL time delay is reached, and must also track the VCC supply level at power-down to prevent unfavorable command sequences. This can be done with pull-up resistors/cs if desired.
After power-up, the device is automatically put into a write-disabled state with the Status Register Write Enable Latch (WEL) set to 0. A Write Enable command must be issued before accepting a Page Program, Sector Erase, Block Erase, Chip Erase, or Write Status Register command. The Write Enable Latch (WEL) is automatically cleared to a write disable state of 0 upon completion of a program, erase or write instruction.
Software-controlled write protection can be simplified using the Write Status Register instruction and setting the Status Register Protection (srp0, srp1) and Block Protection (cmp, sec, tb, bp2, bp1, and bp0) bits. These settings allow part or the entire memory array to be configured as read-only for sectors as small as 4KB. Used in conjunction with the write-protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. See the Status Registration section for more information. In addition, the power-down command provides an extra level of write protection, as all commands except the release power-down command are ignored.

Status Registers and Instructions The Read Status Register-1 and Status Register-2 instructions can be used to provide the status of the flash array availability, if the device is write enabled or disabled, write protection status, quaternary SPI settings, security register lock status and erase/ Program paused state. The Write Status Register command can be used to configure the device write protection feature, quad SPI settings and security register OTP lock. Write access to the status register is controlled by the nonvolatile status register protection bits (srp0, srp1), the state of the write enable instruction, and the /wp pin during standard/dual SPI operation.
Status Register Busy/Busy is a read-only bit in the Status Register (S0) when the device performs a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, or Erase/Program Security Register instruction, this bit is set to 1 state. During this time, the device will ignore instructions other than Read Status Register and Erase/Program Suspend instructions (see tw, tpp, tse, tbe, and tce in AC Characteristics). When a program, erase or write status/secure register instruction completes, the busy bit will be cleared to the 0 state, indicating that the device is ready for further instructions.
Write Enable Latch (WEL) The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that is set to 1 after a Write Enable instruction is executed. When the device is write disabled, the WEL status bit is cleared to 0. A write disable state occurs at power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register, and Program Security Register.
Block Protection Bits (bp2, bp1, bp0) Block Protection Bits (bp2, bp1, bp0) are non-volatile read/write bits in the Status Registers (s4, s3, and s2) that provide write protection control and status. The block protection bits can be set using the Write Status Register instruction (see tw in AC Characteristics). All, all or part of the memory array can be protected from program and erase instructions (see Status Register Memory Protection table). The factory default setting of the block protection bit is 0, which is not array protected.
Top/Bottom Block Protection (TB) The non-volatile top/bottom bit (TB) controls whether the block protection bits (BP2, BP1, BP0) are protected from the top (TB=0) or bottom (TB=1) of the array, As shown in the Status Register Memory Protection table. The factory default setting is tb=0. Depending on the state of the srp0, srp1, and wel bits, the tb bit can be set with the write status register instruction.
Sector/Block Protection (sec) The non-volatile sector/block protection bits (sec) control whether the block protection bits (bp2, bp1, bp0) protect the 4KB at the top (tb=0) or bottom (tb=1) of the array Sectors (sec=1) or 64KB blocks (sec=0), as shown in the Status Register Memory Protection table. The default setting is sec=0.
Complement Protection (CMP) The Complement Protection bit (CMP) is a nonvolatile read/write bit in the Status Register ( S14 ). It is used in combination with the sec, tb, bp2, bp1 and bp0 bits to provide greater flexibility for array protection.

CMP is set to 1, the array protection previously set by SEC, TB, BP2, BP1 and BP0 will be reversed. For example, when cmp=0, the first 4KB sectors can be protected while the rest of the array is unprotected; when cmp=1, the first 4KB sectors will become unprotected and the rest of the array will become Read only. See the Status Register Memory Protection table for details. The default setting is cmp=0.
Status Register Protection (srp1, srp0) The Status Register Protection bits (srp1 and srp0) are non-volatile read/write bits in the Status Register (s8 and s7). The SRP bit controls the method of write protection: software protection, hardware protection, power lock, or one-time programmable (OTP) protection.

Note: 1. When srp1, srp0 = (1, 0), power off, power cycle will change srp1, srp0 to (0, 0) state. 2. This feature is available by special order. Please contact Winbond for details.
Erase/Program Suspend Status (SUS) The Suspend Status bit is a read-only bit in the Status Register (S15) that is set to 1 after the Erase/Program Suspend (75H) instruction is executed. The SUS status bit is cleared to 0 by the Erase/Program Resume (7ah) command and power down and power cycle.
Secure Register Lock Bits (lb3, lb2, lb1) Secure Register Lock Bits (lb3, lb2, lb1) are non-volatile one-time program (otp) bits in the Status Register (s13, s12, s11) that provide secure register Write protection control and status. The default state of LB3-0 is 0 and the security registers are unlocked. lb3-1 can be individually set to 1 using the Write Status Register instruction. LB3-1 is one-time programmable (OTP), once set to 1, the corresponding 256-byte security register will permanently become read-only.
Quaternary Enable (QE) The Quaternary Enable (QE) bit is a non-volatile read/write bit in the Status Register (S9) that allows Quaternary SPI and QPI operations. The /wp pin and /hold are enabled when the QE bit is set to the 0 state (factory default for part numbers with order options "ig" and "if"). When the QE bit is set to 1

For quad enable part numbers with ordering option "IQ", the quad IO2 and IO3 pins are enabled, and the /wp and /hold functions are disabled.
Before issuing "enable qpi(38h)" to switch the device from standard/dual/quad SPI to qpi, the qe bit needs to be set to 1, otherwise the command will be ignored. When the device is in qpi mode, the qe bit will remain 1. The "Write Status Register" command in QPI mode cannot change the QE bit from "1" to "0".
Warning: The QE bit should not be set to 1 if the /wp or /hold pins are connected directly to power or ground during standard SPI or dual SPI operation.

Instructions The standard/dual/quad SPI instruction set of the W25Q64FV consists of 36 basic instructions which are fully controlled via the SPI bus. Instructions start on the falling edge of chip select (/cs). The first byte of data clocked into the DI input provides the instruction code. Data at the DI input is sampled first on the rising edge of the clock, most significant (MSB).
The QPI instruction set of the W25Q64FV consists of 24 basic instructions, which are fully controlled through the SPI bus (see Instruction Set Table 4). Instructions start on the falling edge of chip select (/cs). The instruction code is provided through the first data byte of the IO[3:0] pins. Data on all four IO pins is sampled first on the rising edge of the clock, most significant bit (MSB). All QPI instructions, address, data and dummy bytes use all four IO pins to transfer each data byte every two serial clocks (CLK).
Instructions vary in length from one byte to several bytes, and may be followed by address bytes, data bytes, dummy bytes (unimportant), and in some cases a combination. Use the rising edge of Edge/CS to complete the description. Clock versus timing diagrams for each instruction are included in Figures 5 through 42. All read instructions can be completed after any clock bit. However, all instructions to write, program, or erase must complete on a byte boundary (high bits driven by CS after a full 8-bit has been clocked), otherwise the instruction will be ignored. This feature further prevents accidental writes to the device. Additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except read status register are ignored until the program or erase cycle is complete.