The CDCVF2509 is a high performance, low skew, low jitter, phase locked loop (PLL) clock driver. It uses a PLL to precisely align the feedback (FBOUT) output to the clock (CLK) input signal in frequency and phase. It is specifically designed for synchronous DRAM. The CDCVF2509 operates from 3.3 V VCC. It also offers integrated series damping resistors, making it ideal for driving point-to-point loads. A set of five outputs and a set of four outputs provide nine low-skew, low-jitter copies of CLK. The output signal duty cycle is adjusted to 50%, independent of the duty cycle of CLK. Each group of outputs is enabled or individually disabled via the control (1G and 2G) inputs. When the G input is high, the output switches in-phase and the frequency is the same as CLK; when the G input is low, the output is disabled to a logic low state. Unlike many products that include a PLL, the CDCVF2509 does not require an external RC network. The loop filter PLL is packaged on-chip, minimizing component count, board space, and cost. Because it is based on a PLL circuit, the CDCVF2509 requires a settling time to phase lock the feedback signal to the reference signal. This settling time CLK is required after power-up and application of a fixed frequency, fixed phase signal, and any changes in the PLL reference or feedback signal. The PLL can be bypassed by tying AVCC to ground. The CDCVF2509A features an operating temperature range of 0°C to 85°C.

application

PLL based clock distributor

Non-PLL Clock Buffer

feature

66 MHz to 66 MHz static phase error distribution 166 MHz is ±125 ps

66 MHz to 166 MHz jitter (cyc - cyc) Typ = 70 ps

Advanced deep submicron process results in more than 40% lower power consumption versus contemporary PC133 devices

Available in plastic 24-pin TSSOP package

Phase-locked loop clock distribution for synchronous DRAM applications

Assign a clock input to a bank of five and a set of four outputs

Output enable bank separately for each output

Synchronize output to clock input using external feedback (FBIN) terminal

PW PACKAGE (top view)

Functional block diagram

Not recommended for new designs, use CDCVF2509A as a replacement

pin function

clock input. CLK provides the clock signal distributed by the CDCVF2509A clock driver. CLK

Used to provide a reference signal to an integrated PLL that generates the clock output signal.

CLK 24 I CLK must have a fixed frequency and a fixed phase for the PLL to obtain phase lock. Once the circuit

Power up and apply a valid CLK signal, the PLL needs settling time to phase

Lock the feedback signal to its reference signal.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired

FBIN 13 I FBOUT completes the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

Nominally zero phase error between CLK and FBIN.

Output library enabled. 1G is the output enable that outputs 1Y (0:4). When 1G is low, output 1Y (0:4)

1G 11 I is disabled to logic low state. When 1G is high, all outputs 1Y (0:4) are enabled and switched to

Same frequency as CLK.

Output library enabled. 2G is the output enable that outputs 2Y (0:3). When 2G is low, output 2Y (0:3)

2G 14 I disable logic low state. When 2G is high, all outputs 2Y (0:3) are enabled and switched to

Same frequency as CLK.

feedback output. FBOUT is dedicated to external feedback. it switches at the same frequency as

FBOUT 12 O CLK. When connected externally to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has

Integrated 25Ω series damping resistor.

clock output. These outputs provide low-skew copies of CLK. Output bank 1Y (0:4) passes

1Y (0:4) 3, 4, 5, 8, 9 and 1G input. These outputs can be disabled to a logic low state by deactivating the 1G control

enter. Each output has an integrated 25Ω series damping resistor.

clock output. These outputs provide low-skew copies of CLK. Output bank 2Y (0:3) passes

2Y (0:3) 16, 17, 21, 20 O at 2Y input. These outputs can be disabled to a logic low state by deasserting the 2G control

enter. Each output has an integrated 25Ω series damping resistor.

Analog power. AVCC provides the power reference for analog circuits. In addition, AVCC

AVCC 23 Power can be used to bypass the PLL. When AVCC is grounded, PLL is bypassed and CLK is bypassed

Buffered directly to the device output.

AGND 1 Ground analog ground. AGND provides the ground reference for analog circuits.

VCC 2,10,15,22 Power

GND 6,7,18,19 Ground

Absolute Maximum Ratings

AVCC supply voltage range (2) AVCC

VCC supply voltage range -0.5 V to 4.3 V.

VI

Input voltage range (3) -0.5 V to 4.6 V.

VO voltage range for any output in high or low state (3) (4) -0.5 V to VCC + 0.5 V

IIK Input Clamping Current (VI < 0) - 50 mA

IOK output clamp current (VO < 0 or VO > VCC) ±50 mA

IO continuous output current (VO = 0 to VCC) ±50 mA

Continuous current through each VCC or GND ±100 mA

Maximum power dissipation (in still air) at TA = 55°C (5) 0.7 W

Tstg storage temperature range is -65°C to 150°C

(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device under these or any other conditions beyond those indicated in "Recommended Operation Conditions" is not implied. Prolonged exposure to absolute maximum rated conditions may affect device reliability.

(2) AVCC must not exceed VCC + 0.7 V.

(3) Input and output negative voltage ratings may be exceeded if input and output clamp current ratings are observed.

(4) The value is limited to a maximum of 4.6 V.

(5) Maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

Parameter measurement information

output load circuit

Voltage waveform propagation delay time

Skew calculation graph