illustrate
The WM8974 is a low power, high quality mono codec designed for portable applications such as digital cameras or digital audio recorders.
The device integrates support for differential or single-ended microphones, including drivers for speakers or headphones, and mono output. External component requirements are reduced as no separate microphone or headphone amplifier is required.
Advanced Sigma-Delta converters are used with digital decimation and interpolation filters to provide high quality audio at sample rates from 8 to 48ks/s. Additional digital filtering options are provided in the ADC path to suit application filtering such as "wind noise reduction", pl we provide an advanced mixed-signal ALC function with noise gate. The digital audio interface supports a-law and law compression.
The present invention provides an on-chip PLL for generating the required master clock from an external reference clock. The PLL clock can also be output if needed elsewhere in the system.
The WM8974 operates from a supply voltage of 2.5 to 3.6V, although digital supplies can operate at 1.71V to save power. The speaker and mono outputs use independent power supplies up to 5 volts to increase output power when needed. Different parts of the chip can also be shut down under software control via a selectable two- or three-wire control interface.
Housed in a very small 4x4mm QFN package, the WM8974 offers a high level of functionality in a minimal board area with high thermal performance.
Features Single Codec: Audio Sample Rate: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 98db, THD-84db ('A'-weighted @8–48ks/s) ADC Signal-to-noise ratio 94db, THD-83db ('A'-weighted @8–48ks/s)  On-chip headphone/speaker driver with 'capless' connection - 40MW output power converted to 16'/3.3V spkvdd-BTL speaker Drives 0.9W, input 8≠/5V spkvdd  Additional single line output  Multiple analog or "aux" inputs, plus analog bypass path Microphone preamp:  Differential or single-ended microphone interface - programmable preamp gain - Psuedo Differential Input Rejection with Common Mode - Programmable ALC/Noise Gate in ADC Path Low Noise Bias for Electret Microphone Additional Features 5 Band EQ (Record or Playback Path) Digital Playback Limiter Available Programmable ADC high pass filter (wind noise reduction) Programmable ADC notch filter On-chip PLL Low power, low voltage -2.5V to 3.6V (Digital: 1.71V to 3.6V) - Power consumption <10mA , all in 48K/S mode  4x4x0.9mm 24-wire QFN software package application  Digital camera audio codec  Wireless VoIP and other communication phone/headset  Portable voice recorder  Universal low power audio codec control

Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. Continuous operation at or above these limits may cause permanent damage to the equipment. The functional operating limits and guaranteed performance specifications of the device are given under the electrical characteristics under the specified test conditions.
Electrostatic discharge sensitive devices. The device is fabricated on a CMOS process. Therefore, it is generally susceptible to damage by excessive static voltages. Appropriate antistatic measures must be taken when handling and storing this unit.
Cirrus Logic conducts moisture sensitivity testing of its packaging types in accordance with IPC/JEDEC J-STD-020B to determine acceptable storage conditions prior to surface mount assembly. These levels are: msl1 = infinite floor life at less than 30 degrees Celsius / 85% relative humidity. Usually not stored in moisture-proof bags. msl2 = 1 year out-of-bag storage below 30°C/60% RH. A moisture-proof bag is provided. msl3 = 168 hours out-of-bag storage below 30°C/60% RH. A moisture-proof bag is provided.
The moisture sensitivity level for each packaging type is specified in the ordering information.
the term
1. Enter micn only in single-ended mic configurations. The maximum input signal without distortion is -3dbv.
2. Hold time is the length of time between when the detected signal is too quiet and when the gain begins to increase. It is not suitable for lowering the gain when the signal is too large, i.e. without delay.
three. Ramp-up and ramp-down times are defined as the time it takes for the PGA to change its gain by 6db.
4. All hold, rise and fall times are proportional to MCLK
5. Signal-to-Noise Ratio (db) – Signal-to-noise ratio is a measure of the difference in level between the full-scale output and the unapplied signal output. (Achieve these results without using autozero or auto functions).
6. THD+N (db) – THD+N is the ratio of (noise + distortion) / rms value of the signal.
7. The speaker power supply can limit the maximum output voltage. If monobost=1, spkvdd should be 1.5xavdd or higher to prevent clipping during the output stage.

Device Description Introduction
The WM8974 is a low-power audio codec that combines a high-quality mono audio DAC and ADC with flexible line and microphone input and output processing. Applications for this device include digital cameras with mono audio, recording and playback capabilities, voice recorders, wireless VoIP headsets, and game console accessories.
The chip has great flexibility of use, so it can support many different modes of operation, as follows:
Microphone Input provides two microphone inputs, allowing connection of differential microphone inputs or single-ended microphones. These inputs have a user programmable gain range of -12db to +35.25db using internal resistors. After the input PGA stage, there is a boost stage that can further increase the gain by 20dB. Output the microphone bias voltage from the chip, which can be used to bias the microphone. Signal routing can be configured to allow manual adjustment of the microphone level, or to allow the ALC loop to control the transmitted microphone signal level.
The total gain through the microphone path can be selected up to +55.25db.
PGA and ALC operations provide programmable gain amplifiers in the input channels of the ADC. This can be used manually or in combination with a hybrid analog/digital automatic level control (ALC) that keeps the recording volume constant.
Auxiliary Inputs The device includes a mono input, AUX, which can be used as an input for warning tones (BEEP), etc. The output of this circuit can be aggregated into a mono output and/or a speaker output path to mix the audio with "background music" etc. as needed. This path can also be flexibly summed to the input, or to the input PGA as a second mic input or line input. The circuit's configuration with integrated on-chip resistors allows several analog signals to be aggregated to a single auxiliary input when required.
Analog-to-digital converter The mono ADC uses a multi-bit high-order oversampling structure to provide the best performance at low power consumption. Various sample rates are supported, from the 8ks/s rate commonly used in speech dictation to the 48ks/s rate used in high-quality audio applications.
Hi-Fi Digital-to-Analog Converter Hi-Fi DAC provides high-quality audio playback suitable for all portable mono audio type applications.
Digital Filtering Advanced Sigma-Delta converters are used in conjunction with digital decimation and interpolation filters to provide high quality audio at sample rates from 8ks/s to 48ks/s.
In addition, application-specific digital filters are available to help reduce the effects of specific noise sources such as "wind noise". The filters include a programmable ADC high pass filter, a programmable ADC notch filter and a 5-band equalizer that can be applied to the ADC or DAC path to improve the overall audio sound from the device.
The output of the output mixing and volume adjustment device provides flexible mixing; the speaker output provides a mixer, and the mono output provides additional mono summer. These mixers allow combining the output of the DAC, the output of the ADC volume control, and the auxiliary input. The output volume can be adjusted using the integrated digital volume control, and the speaker output has additional analog gain adjustment.
audio port
WM8974 has a standard audio interface, which supports the transmission of audio data between chips. This interface is a 4-wire standard audio interface that supports many audio data

Formats include I2s, DSP mode, MSB first, left justified and MSB first, right justified, and can operate in master or slave mode.
Control Interface To achieve full software control of all functions, the WM8974 provides a choice of 2-wire or 3-wire MPU control interface. It is fully compatible and is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the mode pin. If the mode is high, the 3-wire control mode is selected; if the mode is low, the 2-wire control mode is selected.
In 2-wire mode, only slave operation is supported, and the device address is fixed at 0011010.
clock scheme
The WM8974 provides normal audio DAC clocking scheme operation where the 256fs MCLK is provided to the DAC/ADC.
However, a PLL is also included, which can be used to generate the internal master clock frequency when the system controller cannot provide it. The PLL uses an input reference (usually a 12MHz USB clock) to generate a high quality audio clock. If the PLL is not required to generate these clocks, it can be reconfigured to generate alternate clocks that can then be output on the CSB/GPIO pins and used elsewhere in the system.
Power Control
The design of the WM8974 places great emphasis on power consumption without compromising performance. It operates on low supply voltages, including devices that shut down any unused parts of the circuit under software control, including standby and shutdown modes.
input signal path
The WM8974 has 3 flexible analog inputs: two microphone inputs and one auxiliary input. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block that then feeds the gain boost/mixer stage.
Microphone Input The WM8974 can accommodate a variety of microphone configurations, including single-ended and differential inputs. Inputs through MICN, MICP, and optional AUX pins are amplified by the input PGA pseudo-differential input is the preferred configuration, where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. Then, the microphone ground should be connected to the MICN (when MICN2INPPGA=1) or AUX (when AUX2INPPGA=1) input pin.
Alternatively, you can connect a single-ended microphone to the micn input and set micn2inppga to 1. The non-inverting terminal of the input PGA should be internally connected to VMID by setting MICP2INPPGA to 0.
In differential mode, the larger signal should go to the MICP and the smaller (eg, noisy ground connection) should go to the MICN.

Peak Limiter To prevent large signals from clamping after a period of silence, the automatic height control circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16db), the PGA gain decreases at the maximum attack rate (when alcatk=0000) until the signal level falls below 87.5% of full scale. This feature is automatically enabled when ALC is enabled.
Note: If alcatk=0000, the limiter has no effect on the operation of the alc. It is designed to prevent the use of clips for long attack times.
Noise Gate (Normal Mode only)
When the signal is very quiet and consists mostly of noise, the ALC function can cause "noise pumping", a loud hissing sound during periods of silence. The WM8974 has a noise gate function that prevents noise pumping by comparing the signal level at the input with the noise gate threshold (length). The noise gate opens when:
Signal level at ADC [dbfs] < length [dbfs] + PGA gain [db] + microphone boost gain [db]
This is equivalent to:
Input signal level [dbfs] Then, the PGA gain remains the same (preventing it from rising like it normally does when the signal is quiet).
The following table summarizes the noise gate control registers. The length control bits set the noise gate threshold relative to the full-scale range of the ADC. Thresholds are adjusted in 6db steps. Extreme levels of the range may result in inappropriate operation, so care should be taken with the settings of the function. The noise gate only works with automatic height control, not in limiter mode.

output signal path
The WM8974 output signal path consists of a digital application filter, an upsampling filter, a high-fidelity digital-to-analog converter, an analog mixer, a speaker, and a mono output driver. Digital filters and digital-to-analog converters are enabled by digital-to-analog converters. The mixer and output drivers can be individually enabled by separate control bits (see Analog Outputs). Therefore, the analog mixing and amplification provided by the WM8974 can be used regardless of whether the DAC is running.
The WM8974 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions:
Digital Volume Control Graphic Equalizer Digital Peak Limiter. Sigma delta modulation The high-performance Sigma Delta audio DAC converts digital data to analog.

The digital limiter operation limiter has a programmable upper limit close to 0db. Referring to Table 28, in normal operation (limboost=000=>value only), signals below this threshold are not affected by the limiter. Signals above the threshold are attenuated at a specific attack rate (set by the limatk register bits) until the signal falls below the threshold. The limiter also has a lower limit of 1db below the upper limit. When the signal is below the low threshold, the signal is amplified at a specific decay rate (controlled by the limdcy register bits) until a gain of 0db is reached. Both threshold levels are controlled by the limlvl register bits. The upper threshold is 0.5db higher than the value programmed by limlvl, and the lower threshold is 0.5db lower than the limlvl value.
The Volume Up Limiter has a programmable upper gain, which boosts the signal below a threshold to compress the signal's dynamic range and increase its perceived loudness. It works as an automatic altitude control feature with limited augmentation capabilities. The volume boost is from 0db to +12db, step by 1db, controlled by the limbboost register bit.
When the limiter is disabled, the output limiter volume boost can also be used as an independent digital gain boost.

The mono and speaker outputs have output driver stages controlled by register bits monoboost and spkboost, respectively. Each output stage has a selectable gain amplification of 1.5x. When this amplification is enabled, the output DC level is also level shifted (from AVDD/2 to 1.5XAVDD/2) to prevent signal clipping. As shown in Figure 20, a dedicated amplifier is used to perform the DC level shifting operation. For this mode of operation, this buffer must be enabled using the bufdcopen register bit. It should also be noted that this boost mode may cause signal clipping if spkvdd is not equal to or greater than 1.5xavdd.

There is a dedicated buffer for bundling unused analog I/O pins. This buffer can be enabled using the bufioen register bits.
If the SPKboost or monoboost bit is set, the associated output will be associated with the 1.5xavdd/2 DC level-shift buffer output when disabled.

Output Switch When the device is configured with a 2-wire interface, the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker output and enable the mono output. For example, when the line is plugged into an outlet. In this mode, enabled by setting gpiosel=001, the pin csb/gpio switch between mono and speaker output (eg when pin 12 is connected to a mechanical switch in the headphone jack to detect plug-ins). The gpiopol bit inverts the polarity of the csb/gpio input pins.
Note that the speaker output and mono output must be enabled, in this mode the CSB/GPIO pin has an internal debounce circuit to prevent multiple toggling of the output enable due to input glitches. The debounce circuit is clocked from a slow clock with a period of 221 x mclk, enabled using the slowclken register bit.

Digital Audio Interface The audio interface has four pins: ADCDAT: ADC data output DACDAT: DAC data input Frame: Data alignment clock , can also be entered when operating as a slave (see Master and Slave Mode Operation below).
Four different audio data formats are supported: Left justified  Right justified  I2s  DSP mode All of these modes are MSB first. They are described in audio data format as shown below. See the Electrical Characteristics section for timing information.
Master and Slave Operation The WM8974 audio interface can be configured as a master or slave. As a master interface device, the WM8974 generates BCLKs and frames that control the sequence of data transfers on ADCDAT and DACDAT. To set the device to master mode, register bit ms should be set high. In slave mode (ms=0), the clock response data received by WM8974 through the digital audio interface.
Audio data format In left justified mode, the MSB can be used on the first rising edge of BCLK after a frame transition. Then, the other bits arriving at the LSB are transmitted sequentially. Depending on word length, BCLK frequency, and sample rate, there may be unused BCLK cycles before each frame conversion.
Master Clock and Phase Locked Loop (PLL)
The WM8974 features an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate the master clock for the WM8974 audio functions from another external clock (such as in telecom applications).
Generate and output (on pin CSB/GPIO) a clock for the rest of the system derived from the existing audio master clock.
The PLL can be enabled or disabled by the PLLEN register bits.
Note: To minimize current consumption, the PLL is disabled when the vmidsel[1:0] bits are set to 00B. vmidsel[1:0] must be set to a value other than 00B to enable the PLL.

2-wire serial control mode
The WM8974 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is different from the 7-bit address of each register in the WM8974).
The WM8974 works only as a slave device. While SCLK is held high, the controller indicates the start of a data transfer with a high-to-low transition on SDIN. This means that the device address and data will follow. All devices on the 2-wire bus respond to the start condition and move the next 8 bits (7-bit address + read/write bits, MSB first) on SDIN. If the received device address matches that of the WM8974, the WM8974 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognized or the R/W bit is "1" when operating in write-only mode, the WM8974 returns to the idle state, waiting for a new start condition and a valid address.
During the write process, once the WM8974 has confirmed the correct address, the controller sends the first byte of control data ( B15 to B8, the WM8974 register address plus the first bit of register data). The WM8974 then acknowledges the first data byte by pulling sdin low for one clock pulse. Then, the controller sends the second byte of control data (b7 to b0, the remaining 8 bits of the register data), which the WM8974 confirms again by pulling sdin low.
The transfer is complete when there is a low-to-high transition on SDIN while SCLK is high. After completing the sequence, the WM8974 returns to the idle state, waiting for another start condition. If at any point during a data transfer a start or stop condition is detected out of sequence (i.e. a change in SDIN while SCLK is high), the device will transition to the idle state.
The reset chip can reset the WM8974 by writing any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this, there is a power-on-reset (PoR) circuit, which ensures that the registers are set to their default values when the device is powered up.
power supply
The WM8974 can use up to four independent power supplies:
AVDD and AGND: Analog supplies, powering all analog functions except speaker output and mono output driver. AVDD ranges from 2.5V to 3.6V and has the greatest impact on overall power consumption (except for headphone power consumption). A larger AVDD slightly improves audio quality.
spkvdd and spkgnd: Headphone and speaker power supplies, powers the speaker and mono output drivers. SPKVDD can be between 2.5V and 5.5V. SPKVDD can be connected to AVDD, but it requires separate layout and decoupling capacitors to suppress harmonic distortion. With larger SPKVDD, larger headphone and speaker outputs can be achieved with lower distortion. If spkvdd is lower than avdd (or 1.5 x avdd for enhanced mode), the output signal may be truncated.
DCVDD: Digital core power supply, powers all digital functions except audio and control interfaces. The voltage range of DCVDD is from 1.71V to 3.6V with no effect on audio quality. The return path of dcvdd is dgnd, which is shared with dbvdd.
DBVDD ranges from 1.71V to 3.6V. The DBVDD return path is through DGND.
The same supply voltage can be used for all four supplies. However, the digital and analog power supplies should be routed and separated separately on the printed circuit board to prevent digital switching noise from entering the analog signal path.
Note: When using PLL, DCVDD should be greater than or equal to 1.9V. DCVDD is less than or equal to DBVDD
Recommended Up/Down Power Supply To minimize output pop and click noise, it is recommended to power up and power down the WM8974 device using one of the following sequences:
Power up when not using the output 1.5x boost stage:
1. Turn on external power. Wait for the power supply voltage to stabilize.
2. Set biasen=1, bufioen=1, and the vmidsel[1:0] bits in the power management 1 register. *Notes 1 and 2.
three. Wait for the VMID supply to settle. *Note 2.
4. Enable dac by setting dacen=1.
5. Enable blender as needed.
6. Enable output stages as needed.
Power up when using the output 1.5x boost stage:
1. Turn on external power. Wait for the power supply voltage to stabilize.
2. Enables 1.5x output enhancement. Set monoboost=1 and spkboost=1 as desired.

three. Set biasen=1, bufioen=1, bufdcopen=1, and the vmidsel[1:0] bits in the power management 1 register. *Notes 1 and 2.
4. Wait for the VMID supply to settle. *Note 2.
5. Enable dac by setting dacen=1.
6. Enable blender as needed.
7. Enable output stages as needed.
Power outage (all cases):
1. Soft mute the dac by setting dacmu=1.
2. Disable power management register 1 by setting r1[8:0]=0x00.
three. Disable all other output stages.
4. Turn off external power.
notes:
1. This step enables the internal device bias buffer and vmid buffer for unallocated input/output. This will provide the start-up reference voltage for all inputs and outputs. This will cause the input and output to ramp in a controllable and predictable manner towards VMID (without output 1.5x boost) or 1.5x (AVDD/2) (with output 1.5x boost) (see Note 2).
2. Select the value of the vmidsel bit according to the start-up time (vmidsel=10 means the slowest start, vmidsel=11 means the fastest start). The startup time is defined by the value of the vmidsel bit (reference impedance) and an external decoupling capacitor on vmid.
In addition to the power-up sequence, it is recommended to use the zero-crossing feature when changing the volume in the PGA to avoid hearing any pops or clicks.

notes:
1. The analog input pin charging time tmidrail_on is determined by the vmid pin charging time. This time depends on the value of the VMID decoupling capacitor and the input resistance of the VMID pin and the AVDD supply rise time.
2. The analog input pin discharge time, tmidrail_off, is determined by the analog input coupling capacitor discharge time. The time that TmidRail is open is measured using a 1µF capacitor at the analog input, but varies with the value of the input coupling capacitor.
three. When the ADC is enabled, there will be LSB data bit activity on the ADCDAT pin due to system noise, but no noticeable digital output will appear.
4. The vmidsel and biasen bits must be set to enable the analog input IF voltage and normal ADC operation.
5. The ADCDAT data is delayed from the power supply -P- output, and the power supply starts from -V-, mainly determined by the VMID charging time. The ADC initialization and power management bits can be set immediately after the POR is released; the VMID charge time will be significantly longer and indicate when the device is stable for analog input.
6. The ADCDAT data output delay when the device is powered on in standby (power is on) is determined by the ADC initialization time 2/fs.

notes:
1. The line output charging time tLine_Midrail_on is mainly determined by the VMID pin charging time. This time depends on the value of the VMID decoupling capacitor and the input resistance of the VMID pin and the AVDD supply rise time. The above values were measured using a 4.7µF capacitor.
2. It is not recommended to allow DACDAT data input during initialization of the DAC. This can cause popping noise on the analog output if the DAC data value at the initialization point is non-zero. The same is true if DACDAT is removed with a non-zero value and no mute function has been applied to the signal beforehand.
three. Outgoing wire discharge time, ie neutral disconnection, depends on the value of the outgoing coupling capacitor and the leakage resistance path to ground. The above values are measured using a 10µF output capacitor.
4. The headphone charge time, which is the THP mid-rail, depends on the value of the VMID decoupling capacitor and the input resistance of the VMID pin and the AVDD supply rise time. The above values were measured using a 4.7µF VMID decoupling capacitor.
5. The headphone discharge time, ie the THP middle rail is disconnected, depends on the value of the headphone coupling capacitor and the leakage resistance path to ground. The above values were measured using a 100µF capacitor.
6. The vmidsel and biasen bits must be set to enable the analog output IF voltage and normal DAC operation.