Features

Suitable for car applications

ratio conversion

Single power supply: 2.7V to 5V

123] The conversion rate of up to 125KHz

serial interface

#8226; 2 auxiliary analog input

Complete power off control

Personal digital assistant

# 8226; Portable Instrument

Sales point terminal

Porch

touch screen display

Instructions

ADS7843-Q1 is a 12-bit sampling mold converter (ADC) with synchronous serial interface and low-pass blocking switch to drive the touch screen. Under the 125kHz throughput and+2.7V power conditions, the typical power consumption is 750 μW. The reference voltage (VREF) can change between 1V and+VCC, providing the corresponding input voltage range of 0V to VREF. The device includes a shutdown mode that can reduce the typical power consumption to less than 0.5 μW. The operating voltage of ADS7843-Q1 is 2.7V.

Low power consumption, high-speed and board switches make ADS7843-Q1 an ideal choice for battery power supply systems, such as personal digital assistants with resistance touch screens and other portable devices. ADS7843-Q1 is encapsulated by SSOP-16, with a temperature range of -40 ° C to+85 ° C.

Order information

(1), the latest software package and ordering information, please refer to the end of this file Software options appendix.

Typical features

TA u003d 25 ° C, VDD u003d 5 V (unless there are other instructions).

Operation theory ADS7843-Q1 is a typical approaching register (SAR) ADC one by one. This structure is based on capacitance and re -distribution, and its inherent sampling and maintenance function. The transformer is made of 0.6 μmCMOS process. The basic operation of ADS7843-Q1 is shown in Figure 12. The device needs an external benchmark and an external clock. Its operating voltage is 2.7V to 5.25V. External reference voltage can be any voltage between 1V and+VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of ADS7843-Q1.

The analog input of the converter is provided by four -channel multi -way relics. The unique configuration of the low -conducting resistance switch allows an unprecedented ADC input channel to provide a power supply, and an attached pin provides ground for external devices. By maintaining the differential input and differential reference structure of the converter, the pitch resistance error of the switch can be eliminated (if this is the source of a specific measurement error).

Input of analog quantity

Input multi-way relics on ADS7843-Q1, differential inputs of ADC and differential benchmarks of the converter, see Figure 13. Table 1 and 2 show the relationship between A2, A1, A0, and SER/DFR control bit and ADS7843-Q1 configuration. The control position is provided by serial passing through the DIN pin. For more information, see the digital interface part of this data table.

When the converter enters the maintenance mode, the voltage difference between the+in and -in input (see Figure 13) is captured on the internal capacitor array. The input current of the analog input terminal depends on the conversion rate of the device. During the sampling, the power supply must be charged to the internal sampling capacitor (usually 25PF). After the capacitor is full, there is no further input current. The charge transmission rate from analog source to the converter is a function of the conversion rate.

Reference input The voltage difference between+ref and —Ref (as shown in Figure 13) settings Simulation input range. ADS7843-Q1 will work within the range of 1V to+VCC. There are several key items about reference input and its wide voltage range. As the reference voltage decreases, the simulation voltage weight of each digital output code also decreases. This is usually called LSB (minimum effective position) size, which is equivalent to 4096 reference voltage removal. As the reference voltage decreases, any offset or gain error in the ADC will increase by the size of LSB. For example, if the offset of a given converter is 2LSB and the reference voltage is 2.5V, it is usually 5LSB and the reference voltage is 1V. In the same case, the actual offset of each device is 1.22mv. Low noise, low noise, low noise, low noise, low noise, low noise power. The voltage entered to the VREF input end is not buffer, and directly drives the (CDAC) section of the capacitor digital modulus converter ADS7843-Q1. Generally, the input current is 13μA, VREF u003d 2.7V, F sampling u003d 125kHz. According to the result of the conversion, the value will change a little. The reference current decreases with the increase of conversion rate and reference voltage. Because in the clock cycle, each clock cycleThe benchmark current will not be reduced quickly.

When measured when the switch drive is opened, there is also a key item about reference. For this discussion, considering the basic operation of ADS7843-Q1 is useful, as shown in Figure 12. This special application shows the device for digital resistance touch screens. By connecting X+input to ADC, open the Y+and Y-drive, digitize the voltage on X+(as shown in Figure 14), you can measure the current Y position of the fixed-point device. For this measurement, the resistance in the X+wire does not affect the conversion (it does affect the stable time, but the resistance is usually small, so don't worry).

However, due to the low resistance between Y+and Y-, the pitch resistance of the Y drive will indeed produce a small difference. In the current outlook, no matter where the pointer device is on the touch screen, it is impossible to achieve 0V input or full scale input because the internal switch will lose some voltage. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, which provides additional error sources. This situation can be remedied, as shown in Figure 15. By setting the SER/DFR bits to low,+reF and – Ref input directly to Y+and Y -. This makes the A/D conversion rate a measure. The result of the conversion is always the percentage of external resistance, regardless of how it changes the relationship between the internal switching resistance. Please note that in the working mode of use, there is an important consideration about power consumption. For more details, please refer to the power consumption part. Regarding the last point of the differential reference mode, it must be used as a+REF voltage source with+VCC, and cannot be used with VREF. You can use high -precision benchmark and single -end reference mode on VREF for measurement without proportional measurement. Alternatively, in some cases, you can directly supply power from the precision benchmark to the converter. Most references can provide sufficient power supply for ADS7843-Q1, but they may not be able to provide sufficient current for external loads (such as resistance touch screens).

Digital interface

FIG. 16 shows the typical operation of ADS7843-Q1 digital interface. This figure assumes that the digital signal source is a microcontroller or digital signal processor with a basic serial interface. Each communication between the processor and the converter consists of eight clock cycles. A complete conversion can be completed through three serial communication, and a total of 24 clock cycles are entered in DCLK input.

The first 8 clock cycle is used to provide control bytes through DIN pin. When the converter has enough information about the following conversion to appropriately sets the input multi -path replica, switch and reference input, the converter enters the collection (sampling) mode. If it is needed, the internal switch is turned on. After three clock cycles, control bytes are completed, and the converter enters the conversion mode. At this point, enter samplingAnd keep entering the maintenance mode, the internal switch may be turned off. The next 12 clock cycle completes the actual A/D conversion. If the ratio ratio (SER/DFR is low), the internal switch is open during the conversion process. The last one of the conversion result requires 13 clock cycles. It also takes three clock cycles to complete the last byte (DOUT will be very low). These will be ignored by the converter.

Control byte

The position and order of the control bits in the control bytes, see Figure 16. Table 3 and Table 4 gives a little bit about these details. That first place, that is, the ""S"" bit, must always be high, and indicate the beginning of the control byte. ADS7843-Q1 will ignore the input on the DIN pin until the starting position is detected. The next three digits (A2-A0) select one or more activated input channels of the input multiplex (see Table 1, Table 2, and Figure 13). The pattern level determines the number of bits of each conversion, 12 (low) or 8 -bit (high).

SER/DFR bit control reference mode: single -end (height) or differential (low). (Differential mode is also known as the ratio mode In a single -end mode, the reference voltage of the converter is always the difference between VREF and GND pins. In the differential mode, the reference voltage is the difference between the switch currently enabled. For multiple information, please refer to Table 1 and Table 2 and Figure 13 to 15. The last two (PD1-PD0) select the power off mode, as shown in Table 5. If both inputs are high, the device is always power-on. If two two. The input is low, and the device enters the power -off mode between the conversion. When a new conversion starts, the device will immediately return to normal operation. You can power on the device without delay. The first conversion will be effective. There are two there. Electricity mode: one is to disable Penirq and the other is to enable Penirq.

Each conversion 16 clocks

The control bit can be stacked with the conversion ""N"" to allow a conversion per 16 clock cycle, as shown in Figure 17. This figure also shows that each byte transmission between the processor and the converter may be and other string of serial transmission between the transmission of the converter and the converter. Serial communication occurred in the periphery equipment.

As long as each conversion is completed within 1.6 milliseconds after startup, this is possible. Otherwise, the signal that is captured in input sampling and keeping the caught may fall to the extent that it sufficient to affect the conversion result. Please note that ADS7843-Q1 is completely powered on, and other serial communication is being converted. 123]

FIG. 19 and 6 provides a detailed timing of ADS7843-Q1 digital interface.

Data format

The output data of ADS7843-Q1 uses a direct binary format, as shown in Figure 18. This figure shows the ideal output code of the given input voltage, which does not include the impact of offset, gain or noise.

8-bit conversion

ADS7843-Q1 provides a 8-bit conversion mode, which can require faster throughput and the number of numbers is not so critical Use. By switching to the 8 -bit mode, the transition is completed for four clock cycles. This can be used together with 12 -bit transmission serial interfaces, or can complete two conversions through three 8 -bit transmission. This not only shorten each conversion (increased by 25%through throughput), but each conversion can actually be performed at a faster clock rate. This is because the internal stability time of ADS7843-Q1 is not so critical, and it is enough to reach more than 8 bits. The clock frequency can be 50%faster. The faster clock rate and less clock cycle are combined to increase the conversion rate by double.

Power loss

ADS7843-Q1 has two main power modes: full power (PD1-PD0 u003d 11B) and automatic power off (PD1- Pd0 u003d 00B). When running at full speed, when it is changed for 16 clocks each time (see Figure 17), ADS7843-Q1 will use most of the time for acquisition or conversion. There is almost no time to shut down automatically. Therefore, the difference between the full power mode and the automatic power off can be ignored. If you only reduce the conversion rate by reducing the frequency of DCLK input, the two modes will remain roughly equal. However, if the DCLK frequency is maintained at the maximum rate during the conversion process, but the frequency of conversion is very low, the difference between the two modes is significant.

FIG. 20 shows the difference between reducing the frequency of DCLK (""zooming"" DCLK to match the conversion rate) or keep DCLK between the highest frequency and reduce the number of conversion times per second. In the latter case, the percentage of the converter's time in the power off mode will increase (assuming the automatic power off mode is in a state of activity).

Another important consideration of power consumption is the reference mode of the converter. In a single -end reference mode, the internal switch of the converter is only opened when the analog input voltage is obtained (see Figure 16). Therefore, external devices (such as resistance touch screens) are only powered on during the collection. In the differential reference mode, external equipment must be powered on the entire collection and conversion period (see Figure 16). If the conversion rate is high, this will greatly increase power consumption.

Layout

The best performance of ADS7843-Q1 should be provided below. However, many portable applications have contradictions in terms of power, cost, size, and weight. Generally speaking, mostPortable devices have quite ""clean"" power and ground, because most internal components have very low power. This situation will mean that the power of less bypass converters and less attention. However, each situation is unique, and the following suggestions should be carefully reviewed.

In order to get the best performance, pay attention to the physical layout of the ADS7843-Q1 circuit. The basic SAR structure is very sensitive to small failures or sudden changes in power supply, benchmark, grounding connection, and digital input. These changes occur in the previous comparator before locking analog output. There are N windows, and large external transient voltage can easily affect the conversion result. This failure may originate from the switching power supply, the nearby digital logic and high -power equipment. The degree of error in digital output depends on the precise time of reference voltage, layout and external events. If the external event changes over time compared to the DCLK input, the error may change.

Considering this, the power of ADS7843-Q1 should be clean and can be bypass well. 0.1 μF Ceramic Capacitor should be as close to the device as possible. If the connection impedance between+VCC and the power supply is high, 1 μF to 10 μF can also be required. Similarly, 0.1 μF should be used to bypass the reference capacitor. If the reference voltage originated from the computing amplifier, it ensures that it can drive by the power container without oscillation. ADS7843-Q1's inhalation power is very small from the benchmark current, but in a short time (during the conversion period, every rising edge of DCLK) puts forward greater requirements for the reference circuit.

ADS7843-Q1 structure has no input input input without input input without input input. When the input is connected to the power supply, this is particularly worthy of attention. Any noise and ripples from the power supply will appear directly in the number result. Although it can be filtered out of high frequency noise, it is difficult to eliminate the voltage changes caused by line frequency (50Hz or 60Hz).

GND pins should be connected to a clean ground point. In many cases, this will be the ""simulation"" ground. Avoid connections to the location of the location of the microcontroller or digital signal processor. If necessary, track from the converter to the power entrance or battery connection point. The ideal layout will include analog ground layer dedicated to converters and related analog circuits.

In a specific case of using a resistor touch screen, pay attention to the connection between the converter and the touch screen. Because the resistance of the resistance touch screen is quite low, the interconnection should be as short and strong as possible. The longer connection will be a source of error, which is very similar to the internal switching resistance. Similarly, when the contact resistance changes with bending or vibration, the loose connection may be an error source.