The DS1642 is 2K x 8 non-volatile static RAM and a full-featured real-time clock, both of which are accessible in a single-byte wide format. Nonvolatile timing RAM is pin and functionally equivalent to all JEDEC standard 2K x 8 SRAMs. The device can also be easily replaced with ROM, EPROM and EEPROM sockets, providing read/write non-volatile and increased real-time clock functionality. Information for this real-time clock resides in the top 8 RAM locations. RTC registers contain year, month, day, week, hour, minute, and second data in 24-hour BCD format. Corrections for day months and leap years are made automatically. The RTC clock registers are double buffered to avoid incorrect data accesses that may occur during clock update cycles. The double-buffered system also avoids the loss of time for the countdown to increment by accessing the data in the time register. The DS1642 also contains power-fail circuitry that deselects the device in the event of an out-of-tolerance VCC supply. This feature prevents data loss from unpredictable system operation brought by low V CC to avoid erroneous access and update cycles.

clock operation

Reading the soft clock while the double-buffered register structure reduces the chance of reading incorrect data, the internal update to the DS1642 clock register should be stopped reading before the data is clocked to prevent transitions during data reading. However, the clock accuracy is not affected during the update of registers that stop the internal clock. When a 1 is written to the read bit, the update of the seventh most significant bit in the control register is aborted. The update is aborted as long as 1 remains in this position. After issuing stop, the registers reflect the count, that is, the day, date and time, which is currently at the moment the halt command is issued. However, the internal clock registers of the double-buffered system continue to be updated so that the clock accuracy is not accessible by data. All DS1642 registers are updated synchronously after the clock status reset. Updates are read bits written to 0 after one second.

set clock

Bit 8 of the control register is the write bit. When the set write bit is 1, like the read bit, it stops updating to the DS1642 register. Users can then load them in 24-hour BCD format with the correct week, date and time data. Reset the write bits to 0, then these values are transferred to the actual clock counter and allow normal operation to resume.

Stop and start the clock oscillator

The clock oscillator can be stopped at any time. To increase shelf life, the oscillator can be turned off to minimize leakage current from the battery. The OSC bits are the MSB for the seconds register. Set it to 1 to stop the oscillator.

Frequency test bit

Bit 6 of the day is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the seconds register for the LSB will switch to 512 Hz. When the seconds register is read out, the DQ0 line will toggle at 512 Hz as long as the acquire condition is still valid (ie CE low, and OE low) and the address seconds register is still valid and stable.

Clock Accuracy

The DS1642 is guaranteed to be timekeeping accurate to within ±1 minute per month, at 25°C. Clock C. Calibrates using special calibrated non-volatile tuning elements from the Dallas Semiconductor factory. The DS1642 requires no additional correction and the temperature offset will have a negligible implementation in most applications. For this reason, the field clock calibration method is not available and unnecessary.